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Kees Vissers

Bio: Kees Vissers is an academic researcher from University of California, Riverside. The author has contributed to research in topics: Compiler & VHDL. The author has an hindex of 2, co-authored 2 publications receiving 65 citations.

Papers
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Proceedings Article
01 Jan 2005
TL;DR: The results show a 6X decrease in performance and a 100X increase in hardware resource usage for the virtual FPGA approach compared to mapping the circuits directly to a physical FFPA.
Abstract: Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures, yielding software portability benefits Researchers previously introduced the concept of a standard hardware binary to achieve similar portability benefits for hardware, using a JIT compiler to compile the hardware binary to an FPGA The JIT compiler includes lean versions of technology mapping, placement, and routing algorithms that implement the standard hardware binary on a simple custom FPGA fabric designed specifically for JIT compilation While developing a custom FPGA may be feasible for some applications, we propose implementing the simple FPGA fabric as a virtual FPGA In this paper, we present a virtual FPGA, described using structural VHDL and thus representing a firm core that a designer can synthesize onto an existing FPGA We synthesized the firm-core virtual FPGA onto Xilinx Spartan physical FPGAs and then mapped 18 benchmark circuits onto the virtual FPGA Our results show a 6X decrease in performance and 100x more hardware resource usage, for the virtual FPGA approach compared to mapping the circuits directly to the physical FPGA fabric While the hardware overhead is large, large commercial FPGA capacities may still mean that some applications can utilize a virtual FPGA approach if portability is more important than resource utilization Furthermore, our work provides a baseline for future virtual FPGA approaches that may reduce the performance or area overhead through various means

42 citations

Proceedings ArticleDOI
20 Feb 2005
TL;DR: In this paper, the authors propose a virtual FPGA compiler for just-in-time (JIT) compilation of a standard hardware binary to enable standard software binaries to execute on different underlying processor architectures.
Abstract: Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures, yielding software portability benefits. We previously introduced the concept of a standard hardware binary to achieve similar portability benefits for hardware, using a JIT compiler to compile the hardware binary to an FPGA. Our JIT compiler includes lean versions of technology mapping, placement, and routing algorithms that implement the standard hardware binary on a simple custom FPGA fabric designed specifically for JIT compilation. While directly implementing a custom FPGA fabric on silicon may be feasible for some applications, we investigated the option of implementing the simple FPGA fabric as a circuit mapped to a physical FPGA - a virtual FPGA. We described our simple fabric in structural VHDL, synthesized the fabric onto a Xilinx Spartan-IIE FPGA, and mapped 18 benchmark circuits onto the resulting virtual FPGA. Our results show a 6X decrease in performance and a 100X increase in hardware resource usage for the virtual FPGA approach compared to mapping the circuits directly to the physical FPGA. For applications in which hardware portability is essential, a designer could leverage the large capacity of current commercially available FPGAs to implement a virtual FPGA with tens of thousands of configurable gates, providing about the same amount of configurable logic as FPGAs produced in the mid 1990s. Nevertheless, the large overheads clearly indicate the need to develop a virtual FPGA approach tuned to physical fabrics in order to reduce the overhead.

25 citations


Cited by
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Proceedings ArticleDOI
29 Apr 2012
TL;DR: ZUMA is an open-source, cross-compatible embedded FPGA architecture that is intended to overlay on top of an existing FPGAs, in essence an ”FPGA-on-an-FPGA.
Abstract: This paper presents the ZUMA open FPGA overlay architecture. It is an open-source, cross-compatible embedded FPGA architecture that is intended to overlay on top of an existing FPGA, in essence an "FPGA-on-an-FPGA." This approach has a number of benefits, including bit stream compatibility between different vendors and parts, compatibility with open FPGA tool flows, and the ability to embed some programmable logic into systems on FPGAs without the need for releasing or recompiling the master net list. These options can enhance design possibilities and improve designer productivity. Previous attempts to map an FPGA architecture into a commercial FPGA have had an area penalty of 100x at best. Through careful architectural and implementation choices to exploit low-level elements of the host architecture, ZUMA reduces this penalty to as low as 40x. Using the VTR (VPR6) academic tool flow, we have been able to compile the entire MCNC benchmark suite to ZUMA. We invite authors of other tool flows to target ZUMA.

115 citations

Proceedings ArticleDOI
08 Oct 2018
TL;DR: AMORPHOS is presented, which encapsulates user FPGA logic in morphable tasks, or Morphlets, which provides isolation and protection across mutually distrustful protection domains, extending the guarantees of software processes.
Abstract: Cloud providers such as Amazon and Microsoft have begun to support on-demand FPGA acceleration in the cloud, and hardware vendors will support FPGAs in future processors. At the same time, technology advancements such as 3D stacking, through-silicon vias (TSVs), and FinFETs have greatly increased FPGA density. The massive parallelism of current FPGAs can support not only extremely large applications, but multiple applications simultaneously as well.System support for FPGAs, however, is in its infancy. Unlike software, where resource configurations are limited to simple dimensions of compute, memory, and I/O, FPGAs provide a multi-dimensional sea of resources known as the FPGA fabric: logic cells, floating point units, memories, and I/O can all be wired together, leading to spatial constraints on FPGA resources. Current stacks either support only a single application or statically partition the FPGA fabric into fixed-size slots. These designs cannot efficiently support diverse workloads: the size of the largest slot places an artificial limit on application size, and oversized slots result in wasted FPGA resources and reduced concurrency.This paper presents AMORPHOS, which encapsulates user FPGA logic in morphable tasks, or Morphlets. Morphlets provide isolation and protection across mutually distrustful protection domains, extending the guarantees of software processes. Morphlets can morph, dynamically altering their deployed form based on resource requirements and availability. To build Morphlets, developers provide a parameterized hardware design that interfaces with AMORPHOS, along with a mesh, which specifies external resource requirements. AMORPHOS explores the parameter space, generating deployable Morphlets of varying size and resource requirements. AMORPHOS multiplexes Morphlets on the FPGA in both space and time to maximize FPGA utilization.We implement AMORPHOS on Amazon F1 [1] and Microsoft Catapult [92]. We show that protected sharing and dynamic scalability support on workloads such as DNN inference and blockchain mining improves aggregate throughput up to 4× and 23× on Catapult and F1 respectively.

98 citations

Proceedings ArticleDOI
21 May 2018
TL;DR: This survey identifies and classify the various techniques and approaches for FPGA virtualization into three main categories: 1)Resource level, 2)Node level, and 3)Multi-node level.
Abstract: FPGA accelerators are being applied in various types of systems ranging from embedded systems to cloud computing for their high performance and energy efficiency. Given the scale of deployment, there is a need for efficient application development, resource management, and scalable systems, which make FPGA virtualization extremely important. Consequently, FPGA virtualization methods and hardware infrastructures have frequently been proposed in both academia and industry for addressing multi-tenancy execution, multi-FPGA acceleration, flexibility, resource management and security. In this survey, we identify and classify the various techniques and approaches into three main categories: 1)Resource level, 2)Node level, and 3)Multi-node level. In addition, we identify current trends and developments and highlight important future directions for FPGA virtualization which require further work.

86 citations

Journal ArticleDOI
TL;DR: There are ample opportunities for future research on Coarse-Grained Reconfigurable Architectures, in particular with respect to size, functionality, support for parallel programming models, and to evaluate more complex applications.
Abstract: With the end of both Dennard's scaling and Moore's law, computer users and researchers are aggressively exploring alternative forms of computing in order to continue the performance scaling that we have come to enjoy. Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between performance and programmability. In this paper, we survey the landscape of CGRAs. We summarize nearly three decades of literature on the subject, with a particular focus on the premise behind the different CGRAs and how they have evolved. Next, we compile metrics of available CGRAs and analyze their performance properties in order to understand and discover knowledge gaps and opportunities for future CGRA research specialized towards High-Performance Computing (HPC). We find that there are ample opportunities for future research on CGRAs, in particular with respect to size, functionality, support for parallel programming models, and to evaluate more complex applications.

65 citations

Proceedings ArticleDOI
24 Oct 2013
TL;DR: This work is presenting a fine-grained FPGA-like overlay architecture which can be implemented in the user logic of various FPGAs families from different vendors, and presenting different optimizations for dramatically reducing the implementation cost of the proposed overlay architecture.
Abstract: Custom instruction set extensions can substantially boost performance of reconfigurable softcore CPUs. While this approach is commonly tailored to one specific FPGA system, we are presenting a fine-grained FPGA-like overlay architecture which can be implemented in the user logic of various FPGA families from different vendors. This allows the execution of a portable application consisting of a program binary and an overlay configuration in a completely heterogeneous environment. Furthermore, we are presenting different optimizations for dramatically reducing the implementation cost of the proposed overlay architecture. In particular, this includes the mapping of the overlay interconnection network directly into the switch fabric of the hosting FPGA. Our case study demonstrates an overhead reduction of an order of magnitude as compared to related approaches.

52 citations