K
Ken Takeuchi
Researcher at University of Tokyo
Publications - 344
Citations - 6897
Ken Takeuchi is an academic researcher from University of Tokyo. The author has contributed to research in topics: NAND gate & Flash memory. The author has an hindex of 34, co-authored 335 publications receiving 6528 citations. Previous affiliations of Ken Takeuchi include Chuo University & Toshiba.
Papers
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Journal ArticleDOI
Organic Nonvolatile Memory Transistors for Flexible Sensor Arrays
Tsuyoshi Sekitani,Tomoyuki Yokota,Ute Zschieschang,Hagen Klauk,Siegfried Bauer,Ken Takeuchi,Makoto Takamiya,Takayasu Sakurai,Takao Someya +8 more
TL;DR: A sensor matrix is realized that detects the spatial distribution of applied mechanical pressure and stores the analog sensor input as a two-dimensional image over long periods of time by integrating a flexible array of organic floating-gate transistors with a pressure-sensitive rubber sheet.
Patent
Semiconductor device and memory system
Ken Takeuchi,Tanaka Tomoharu +1 more
TL;DR: A semiconductor memory device comprises a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number) and a data circuit having m latch circuits for holding data items read from said memory cells.
Patent
Non-volatile semiconductor memory
TL;DR: In this paper, a nonvolatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory array and sense data retrieved from the memory cell arrays.
Patent
Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells
TL;DR: In this article, a data circuit has a plurality of storage circuits, one of which is a latch circuit and the other one is a capacitor, which is used to temporarily store program/read data having two bits or more.
Journal ArticleDOI
A multipage cell architecture for high-speed programming multilevel NAND flash memories
TL;DR: To realize low-cost, highly reliable, high-speed programming, and high-density multilevel flash memories, a multipage cell architecture has been proposed that enables both precise control of the V/sub th/ of a memory cell and fast programming without any area penalty.