Kenji Nakazawa

Bio: Kenji Nakazawa is an academic researcher. The author has contributed to research in topics: Recrystallization (metallurgy) & Amorphous silicon. The author has an hindex of 2, co-authored 2 publications receiving 230 citations.

Recrystallization of amorphous silicon films deposited by low‐pressure chemical vapor deposition from Si2H6 gas

Abstract: This paper investigated the recrystallization of low‐pressure chemical vapor deposition amorphous silicon (a‐Si) films deposited using Si2H6 gas at various substrate temperatures. The grain size of recrystallized films formed from Si2H6 is larger than that formed from SiH4. The maximum grain size is obtained at the substrate temperature of 460 °C, where the nucleation rate is minimum due to the maximum structural disorder of the Si network. The structural disorder is increased not only by lowering the substrate temperature but also by increasing the deposition rate. The field effect mobility of thin‐film transistors (TFTs) using the recrystallized films reaches 120 cm2 V−1 s−1, even though the highest temperature during the TFT fabrication process is only 600 °C.

Effect of substrate temperature on recrystallization of plasma chemical vapor deposition amorphous silicon films

Abstract: The effect of substrate temperature on the recrystallization of plasma chemical vapor deposition amorphous silicon films is investigated. The grain size of polycrystalline silicon films recrystallized at 600 °C increases as the substrate temperature decreases. The enlargement in the grain size is attributed to the decrease in the nucleation rate. The nucleation rate is suppressed by an increase in structural disorder of the Si network. Electrical properties of recrystallized films are improved by the increase in the grain size.

Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization

Abstract: A new low temperature crystallization method for poly-Si TFTs was developed: Metal-Induced Lateral Crystallization (MILC). The a-Si film in the channel area of a TFT was laterally crystallized from the source/drain area, on which an ultrathin nickel layer was deposited before annealing. The a-channel poly-Si TFTs fabricated at 500/spl deg/C by MILC showed a mobility of 121 cm/sup 2//V/spl middot/s, a threshold voltage of 1.2 V, and an on/off current ratio of higher than 10/sup 6/. These electrical properties are much better than TFTs fabricated by conventional crystallization at 600/spl deg/C.

Polycrystalline silicon thin film transistors

Abstract: During the past decade there has been a rapid growth of interest in poly-Si for the active device layer in thin film transistors (TFTS) for active matrix flat-panel displays. Whilst the early work, demonstrating the high carrier mobility of these devices, employed processing temperatures of approximately 1000 degrees C and quartz susbtrates, this was soon followed by the investigation of lower-temperature processes which were compatible with the use of glass substrates. Some of the key aspects of this work are reviewed in this article: the preparation of the material by direct deposition and by crystallization from a-Si precursors, the characterization of the defect-induced trapping states within the material and their passivation, and the present understanding of the TFT leakage current mechanisms. This work is put into the context of the requirements for active matrix liquid-crystal displays, and, with the understanding and control of poly-Si which has been achieved to date, its application in this area can be expected to increase rapidly in the coming years.

Raman spectroscopy of amorphous and microcrystalline silicon films deposited by low‐pressure chemical vapor deposition

Abstract: In this work we used Raman spectroscopy to investigate the structural characteristics of as‐deposited amorphous and micro‐crystalline silicon films. For amorphous silicon films, the order (or disorder) of the silicon network was quantified using properties of the Raman spectra that were related to key deposition conditions. We found that a strong relationship exists between the structural order of the silicon matrix and the deposition temperature and deposition rate. A quantitative model was proposed relating the intensity ratio of transverse optical phonon peak to longitudinal optical phonon peak to the surface diffusion length, a parameter that was calculated from available data. It was found that optimization of the as‐deposited silicon microstructure is possible by selecting deposition conditions yielding peak–ratio values in the vicinity of 0.53. For as‐deposited micro‐crystalline silicon films, Raman spectroscopy was used to estimate the initial crystalline fraction of the film and monitor the cryst...

Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays

Abstract: The fabrication of thin-film-transistor (TFT) devices on a transparent substrate lies at the heart of active-matrix-liquid-crystal-display (AMLCD) technology. This is both good and bad. On one hand it is a difficult task to manufacture millions of intricate semiconductor devices reliably over such large display substrates. On the positive side, AMLCD technology can aspire to become much more than a “display” technology. The idea is as follows: It is possible for one to readily fabricate additional transistors to execute various electronic functions—those that would otherwise be handled by separate large-scale-integration (LSI) and very large-scale-integration (VLSI) circuits—on the periphery of the display. Since this can be done, in principle, with no—or a minimal number of—additional processing steps, substantial cost reduction is possible and significant value can be added to the final product.Doing so and doing it well can ultimately lead to “system-on-glass” products in which the entire electronic circuitry needed for a product is incorporated directly onto a glass substrate. This means that integrated active-matrix liquid-crystal displays (IAMLCDs) have the potential to bypass conventional Si-wafer-based products and may lead TFT technology to compete directly against Si-wafer-based monolithic integrated circuits.

Polycrystalline silicon thin films processed with silicon ion implantation and subsequent solid-phase crystallization: Theory, experiments, and thin-film transistor applications

Abstract: A review is presented of the self‐implantation method which has been developed to achieve high‐quality polycrystalline silicon thin films on insulators with enhanced grain sizes and its applications to thin‐film transistors (TFTs). In this method, silicon ions are implanted into an as‐deposited polycrystalline silicon thin film to amorphize most of the film structure. Depending on ion implantation conditions, some seeds with 〈110〉 orientation remain in the film structure due to channeling. The film is then thermally annealed at relatively low temperatures, typically in the range of 550–700 °C. With optimized process conditions, average grain sizes of 1 μm or greater can be obtained. First, an overview is given of the thin‐film transistor technology which has been the greatest motivation for the research and development of the self‐implantation method. Then the mechanism of selective amorphization by the silicon self‐implantation and the crystallization by thermal annealing is discussed. An analytical mode...