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Kenji Okuma

Bio: Kenji Okuma is an academic researcher from Toshiba. The author has contributed to research in topics: Algebraic torus & Key schedule. The author has an hindex of 4, co-authored 15 publications receiving 77 citations.

Papers
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Patent
11 Jul 2001
TL;DR: Expanded key schedule circuit for common key encryption system in which expanded keys are used in a predetermined order in data randomizing process for encryption and in a reversed order for decryption, comprises round processing circuits connected in series as discussed by the authors.
Abstract: Expanded key schedule circuit for common key encryption system in which expanded keys are used in a predetermined order in data randomizing process for encryption and in a reversed order in data randomizing process for decryption, comprises round processing circuits connected in series. The round processing circuits subject the common key or sub key of a previous stage to a round function to output a sub key. The sub key of the last stage is equal to the common key. The expanded keys are generated from the sub keys.

42 citations

Patent
19 Mar 2009
TL;DR: In this article, a parameter generating device includes an input receiving unit that receives a degree n of an algebraic torus T and an output unit that outputs parameters when it is determined that the cryptosystem is secure.
Abstract: A parameter generating device includes an input receiving unit that receives a degree n of an algebraic torus T including a group G in which a cryptosystem used in a torus-compressed public key cryptosystem is defined, a size W of a finite field F, and a size S of the group G, an extension-degree determining unit that determines an extension degree m of a finite field Fpm in which the algebraic torus T is defined, a first prime-number search unit that searches for a prime number p, a second prime-number search unit that searches for a prime number q, a test unit that checks whether a multiplication value nm is divisible by the prime number q, a security determining unit that determines that the cryptosystem is secure based on the multiplication value nm, and an output unit that outputs parameters when it is determined that the cryptosystem is secure.

8 citations

Patent
04 Mar 2009
TL;DR: In this article, a decryption scheme was proposed to decrypt encrypted data that has been encrypted first data containing plain data, the encrypted data being represented by using an affine representation F(p: a prime number; m: a natural number; exponentiation: exponentiation).
Abstract: A decrypting apparatus that decrypts encrypted data that has been encrypted first data containing plain data, the encrypted data being represented by using an affine representation F_{pm}×F_{pm}*(where p: a prime number; m: a natural number; and : exponentiation) obtains encrypted data represented in a vector format and a secret key corresponding to a public key and judges whether a vector component contained in the encrypted data is the affine representation F_{pm}×F_{pm}*. Further, based on the result of the judging process, the decrypting apparatus maps the vector component onto each of the members of an algebraic torus by forming a decompression map and decrypts the encrypted data mapped onto each of the members of the algebraic torus, by using the secret key, therefore obtains the plain data.

7 citations

Patent
Kenji Okuma1, Mikio Fujii1, Kouichi Ichimura1, Hayato Goto1, Kentaro Torii1 
29 Jul 2005
TL;DR: In this article, the authors present a quantum cash system and a quantum payment system which can inhibit even forgery in which quantum verification information is transformed using inverse transformation data, thus improving security.
Abstract: An aspect of the present invention relates to a quantum cash system and a quantum cash apparatus which can inhibit even forgery in which quantum verification information is transformed using inverse transformation data, thus improving security. In order to allow quantum cash to be validly used, a quantum cash holding apparatus (3) outputs one of the inverse transformation data and then inhibits the output of the other inverse transformation data in a verification list. This prevents the outflow of the other inverse transformation data, required for the forgery of the quantum cash.

5 citations

Patent
12 Jul 2000
TL;DR: In this paper, the extended key is used in reverse order at the time of ciphering and deciphering, respectively, two round functions f1 and fn+1 are set to be inverse functions to each other having the same number of stages from the first stage as that from the last stage.
Abstract: PROBLEM TO BE SOLVED: To provide a ciphering device capable of avoiding the occurrence of a delay time for generating an extended key, and also generating On-the-fly key. SOLUTION: In an extended key generating part 3 of a ciphering device using a common key block ciphering system in which the extended key is used in reverse order at the time of ciphering and deciphering, respectively, two round functions f1 and fn+1 are set to be inverse functions to each other having the same number of stages from the first stage as that from the last stage, respectively. Thus, it is possible to sequentially generate the extended key immediately and also in order of use by using the extended key as an input at the time of both ciphering and deciphering. Moreover, the extended key generation at the time of ciphering is fundamentally the same as that at the time of deciphering.

4 citations


Cited by
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Patent
21 May 2004
TL;DR: In this paper, a data storage and retrieval device and method is described, which includes at least one magnetic storage medium configured to store target data and at least a re-configurable logic device comprising an FPGA coupled to the at least 1 magnetic medium and configured to read a continuous stream of target data therefrom, having been configured with a template or as desired to fit the type of search and data being searched.
Abstract: A data storage and retrieval device and method is disclosed. The device includes at least one magnetic storage medium configured to store target data and at least one re-configurable logic device comprising an FPGA coupled to the at least one magnetic storage medium and configured to read a continuous stream of target data therefrom, having been configured with a template or as otherwise desired to fit the type of search and data being searched. The re-configurable logic device is configured to receive at least one search inquiry in the form of a data key and to determine a match between the data key and the target data as it is being read from the at least one magnetic storage medium. This device and method can perform a variety of searches on the target data including without limitation exact and approximate match searches, sequence match searches, image match searches and data reduction searches. This device and method may be provided as part of a stand-alone computer system, embodied in a network attached storage device, or can otherwise be provided as part of a computer LAN or WAN. In addition to performing search and data reduction operations, this device may also be used to perform a variety of other processing operations including encryption, decryption, compression, decompression, and combinations thereof.

255 citations

Patent
29 Aug 2008
TL;DR: An integrated circuit for data encryption/decryption and secure key management is described in this paper, which is used in conjunction with other integrated circuits, processors, and software to construct a wide variety of secure data processing, storage, and communication systems.
Abstract: An integrated circuit for data encryption/decryption and secure key management is disclosed. The integrated circuit may be used in conjunction with other integrated circuits, processors, and software to construct a wide variety of secure data processing, storage, and communication systems. A preferred embodiment of the integrated circuit includes a symmetric block cipher that may be scaled to strike a favorable balance among processing throughput and power consumption. The modular architecture also supports multiple encryption modes and key management functions such as one-way cryptographic hash and random number generator functions that leverage the scalable symmetric block cipher. The integrated circuit may also include a key management processor that can be programmed to support a wide variety of asymmetric key cryptography functions for secure key exchange with remote key storage devices and enterprise key management servers. Internal data and key buffers enable the device to re-key encrypted data without exposing data. The key management functions allow the device to function as a cryptographic domain bridge in a federated security architecture.

128 citations

Patent
22 Mar 2007
TL;DR: An encryption technique for encrypting a plurality of data blocks of a data segment where the encryption selectively switches between a blockwise independent randomized encryption mode and a cipher block chaining (CBC) encryption mode based on a configurable feedback stride was disclosed in this article.
Abstract: An encryption technique is disclosed for encrypting a plurality of data blocks of a data segment where the encryption selectively switches between a blockwise independent randomized (BIR) encryption mode and a cipher block chaining (CBC) encryption mode based on a configurable feedback stride. A corresponding decryption technique is also disclosed.

124 citations

Patent
Yosef Stein1, Haim Primo1
18 Dec 2002
TL;DR: In this article, a programmable data encryption engine for performing the cipher function of an AES algorithm includes a parallel look-up table system responsive in a first mode to a first data block for implementing an AES selection function and executing the multiplicative inverse in GF -1 ( 2 8 ) and applying an affine over GF( 2 ) transformation to obtain a sub-byte transformation and in a second mode to the subbyte transformation to transform the sub-transformer to get a shift row transformation.
Abstract: A programmable data encryption engine for performing the cipher function of an advanced encryption standard ( AES ) algorithm includes a parallel look-up table system responsive in a first mode to a first data block for implementing an AES selection function and executing the multiplicative inverse in GF -1 ( 2 8 ) and applying an affine over GF( 2 ) transformation to obtain a subbyte transformation and in a second mode to the subbyte transformation to transform the subbyte transformation to obtain a shift row transformation, and a Galois field multiplier for transforming the shift row transformation to obtain a mix column transformation and add a round key resulting in an advanced encryption standard cipher function of the first data block.

100 citations

Patent
29 Jun 2001
TL;DR: In this paper, an encryption scheme for block data is proposed, which consists of a first processing unit randomizing the block data in units of first portions obtained by dividing the block datasets, and a second processing unit diffusing the output from the first unit with respect to a second portion of the block dataset which is wider than the first portion.
Abstract: An encryption apparatus for block data, comprises a first processing unit randomizing the block data in units of first portions obtained by dividing the block data, and a second processing unit diffusing the block data output from the first processing unit with respect to a second portion of the block data which is wider than the first portion. The first processing unit comprises first nonlinear processing units nonlinearly transforming the block data in units of the first portions. The second processing unit comprises a first linear diffusion processing unit linearly diffusing the second portion of the block data. At least one of the first nonlinear processing units comprises second nonlinear processing units nonlinearly transforming the block data in units of the first portions, and a second linear diffusion processing unit linearly diffusing the second portion of the block data.

75 citations