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Kenneth J. Stein

Bio: Kenneth J. Stein is an academic researcher from IBM. The author has contributed to research in topics: Layer (electronics) & CMOS. The author has an hindex of 26, co-authored 82 publications receiving 1980 citations. Previous affiliations of Kenneth J. Stein include Infineon Technologies & GlobalFoundries.


Papers
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Journal ArticleDOI
TL;DR: In this paper, a SiGe NPN HBT with unity gain cutoff frequency (f/sub T/) of 207 GHz and an f/sub MAX/ extrapolated from Mason's unilateral gain of 285 GHz was reported.
Abstract: This paper reports on SiGe NPN HBTs with unity gain cutoff frequency (f/sub T/) of 207 GHz and an f/sub MAX/ extrapolated from Mason's unilateral gain of 285 GHz. f/sub MAX/ extrapolated from maximum available gain is 194 GHz. Transistors sized 0.12/spl times/2.5 /spl mu/m/sup 2/ have these characteristics at a linear current of 1.0 mA//spl mu/m (8.3 mA//spl mu/m/sup 2/). Smaller transistors (0.12/spl times/0.5 /spl mu/m/sup 2/) have an f/sub T/ of 180 GHz at 800 /spl mu/A current. The devices have a pinched base sheet resistance of 2.5 k/spl Omega//sq. and an open-base breakdown voltage BV/sub CEO/ of 1.7 V. The improved performance is a result of a new self-aligned device structure that minimizes parasitic resistance and capacitance without affecting f/sub T/ at small lateral dimensions.

266 citations

Proceedings ArticleDOI
C-H. Lin1, Brian J. Greene1, Shreesh Narasimha1, J. Cai1, A. Bryant1, Carl J. Radens1, Vijay Narayanan1, Barry Linder1, Herbert L. Ho1, A. Aiyar1, E. Alptekin1, J-J. An1, Michael V. Aquilino1, Ruqiang Bao1, V. Basker1, Nicolas Breil1, MaryJane Brodsky1, William Y. Chang1, Clevenger Leigh Anne H1, Dureseti Chidambarrao1, Cathryn Christiansen1, D. Conklin1, C. DeWan1, H. Dong1, L. Economikos1, Bernard A. Engel1, Sunfei Fang1, D. Ferrer1, A. Friedman1, Allen H. Gabor1, Fernando Guarin1, Ximeng Guan1, M. Hasanuzzaman1, J. Hong1, D. Hoyos1, Basanth Jagannathan1, S. Jain1, S.-J. Jeng1, J. Johnson1, B. Kannan1, Y. Ke1, Babar A. Khan1, Byeong Y. Kim1, Siyuranga O. Koswatta1, Amit Kumar1, T. Kwon1, Unoh Kwon1, L. Lanzerotti1, H-K Lee1, W-H. Lee1, A. Levesque1, Wai-kin Li1, Zhengwen Li1, Wei Liu1, S. Mahajan1, Kevin McStay1, Hasan M. Nayfeh1, W. Nicoll1, G. Northrop1, A. Ogino1, Chengwen Pei1, S. Polvino1, Ravikumar Ramachandran1, Z. Ren1, Robert R. Robison1, Saraf Iqbal Rashid1, Viraj Y. Sardesai1, S. Saudari1, Dominic J. Schepis1, Christopher D. Sheraw1, Shariq Siddiqui1, Liyang Song1, Kenneth J. Stein1, C. Tran1, Henry K. Utomo1, Reinaldo A. Vega1, Geng Wang1, Han Wang1, W. Wang1, X. Wang1, D. Wehelle-Gamage1, E. Woodard1, Yongan Xu1, Y. Yang1, N. Zhan1, Kai Zhao1, C. Zhu1, K. Boyd1, E. Engbrecht1, K. Henson1, E. Kaste1, Siddarth A. Krishnan1, Edward P. Maciejewski1, Huiling Shang1, Noah Zamdmer1, R. Divakaruni1, J. Rice1, Scott R. Stiffler1, Paul D. Agnello1 
01 Dec 2014
TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
Abstract: We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um2) memory solution for industry leading ‘scale-out’ processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ∼0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.

137 citations

Proceedings ArticleDOI
17 Jun 2008
TL;DR: In this article, a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2 was demonstrated.
Abstract: For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at Lgate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.

115 citations

Patent
19 Jun 2003
TL;DR: In this article, a method of fabricating and the structure of a micro-electromechanical switch (MEMS) provided with self-aligned spacers or bumps is described, and the spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction.
Abstract: A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.

103 citations

Journal ArticleDOI
TL;DR: The paper reviews the process development and integration methodology, presents the device characteristics, and shows how the development and device selection were geared toward usage in mixed-signal IC development.
Abstract: This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal system-on-a-chip (SoC). The paper reviews the process development and integration methodology, presents the device characteristics, and shows how the development and device selection were geared toward usage in mixed-signal IC development.

100 citations


Cited by
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Journal ArticleDOI

[...]

08 Dec 2001-BMJ
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

33,785 citations

Book
Yuan Taur1, Tak H. Ning1
01 Jan 2016
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

2,680 citations

Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

Book
01 Jun 2003
TL;DR: In this paper, the authors present a comprehensive treatment of lumped elements, which are playing a critical role in the development of the circuits that make these cost-effective systems possible, including inductors, capacitors, resistors, transformers, via holes, airbridges, and crossovers.
Abstract: Due to the unprecedented growth in wireless applications over the past decade, development of low-cost solutions for RF and microwave communication systems has become of great importance. This practical new book is the first comprehensive treatment of lumped elements, which are playing a critical role in the development of the circuits that make these cost-effective systems possible. The books offers you an in-depth understanding of the different types of RF and microwave circuit elements, including inductors, capacitors, resistors, transformers, via holes, airbridges, and crossovers. Supported with over 220 equations and more than 200 illustrations, it covers the practical aspects of each element in exceptional detail. No other single volume treats this subject matter in such depth. From materials, fabrication, and analyses - to design, modeling, and physical, electrical, and thermal applications, this unique resource offers you complete coverage of the critical topics you need understand for your work in the field. Offering the most comprehensive, up-to-date body of knowledge on lumped elements, the book is an indispensable professional reference and serves as an excellent text for senior undergraduate and graduate-level courses in RF and microwave circuit design.

840 citations

Journal ArticleDOI
J.R. Long1
TL;DR: A comprehensive review of the electrical performance of passive transformers fabricated in silicon IC technology is presented, and the characteristics of two-port and multiport transformers and baluns are presented from both computer simulation and experimental measurements.
Abstract: A comprehensive review of the electrical performance of passive transformers fabricated in silicon IC technology is presented. Two types of transformer construction are considered in detail, and the characteristics of two-port (1:1 and 1:n turns ratio) and multiport transformers (i.e., baluns) are presented from both computer simulation and experimental measurements. The effects of parasitics and imperfect coupling between transformer windings are outlined from the circuit point of view. Resonant tuning is shown to reduce the losses between input and output at the expense of operating bandwidth. A procedure for estimating the size of a monolithic transformer to meet a given specification is outlined, and circuit examples are used to illustrate the applications of the monolithic transformer in RF ICs.

780 citations