Showing papers by "Kenneth Steiglitz published in 1983"
Proceedings Article•
01 Jan 1983
113 citations
TL;DR: The authors specify a design first for a pipelined parallel counter, and then for a complete multiplier that is optimal with respect to both its period and latency, and compares favorably with other recent VLSI multiplier designs.
Abstract: Parallel counters (unary-to-binary converters) are the principal component of a dadda multiplier. The authors specify a design first for a pipelined parallel counter, and then for a complete multiplier. As a result of its structural regularity, the layout is suitable for use in a VLSI implementation. They analyze the complexity of the resulting design using a VLSI model of computation, showing that it is optimal with respect to both its period and latency. In this sense the design compares favorably with other recent VLSI multiplier designs. 24 references.
62 citations
TL;DR: It is shown that, asymptotically, the area required for power distribution actually dominates the rest of the area for a wide class of structures, illustrating the importance of studying the constants of proportionality in evaluating area, time, and energy requirements.
Abstract: A class of completely-pipelined VLSI architectures is defined. Two topologies are then described: leaf-connected trees and mesh-connected trees. The leaf-connected tree structure is used to construct a completely-pipelined bit-serial multiplier and a completely-pipelined word-serial, bit-serial convolver. The mesh-connected tree structure is used to implement completely-pipelined bit-parallel multiplication and completely-pipelined word-parallel bit-parallel convolution. Layouts are described that are within log factors of asymptotic optimality. It is shown that, asymptotically, the area required for power distribution actually dominates the rest of the area for a wide class of structures. This illustrates the importance of studying the constants of proportionality in evaluating area, time, and energy requirements, and suggests that the choice of topologies may very well depend on the fabrication technology. The importance of parameterized and high-level design is stressed throughout. Also stressed is the idea of applying sound architectural technique at all levels of information organization, including, in particular, the bit level.
39 citations
14 Apr 1983
TL;DR: The problem of designing lowpass FIR digital filters that are very flat at zero frequency, smooth in the passband, and minimax in the stopband is treated.
Abstract: We treat the problem of designing lowpass FIR digital filters that are very flat at zero frequency, smooth in the passband, and minimax in the stopband. The cases of lowpass and lowpass-differentiator are studied in particular. An effective design algorithm is described based on linear programming with a single equality constraint on the first derivative at the origin plus a concavity constraint in the passband. An empirical design equation for estimating model order in the odd-length lowpass-differentiator case is given.
26 citations
01 Apr 1983
TL;DR: The results show that significant reductions in AP-product can be achieved by-intermediate latching in many typical signal processing applications, for a wide range of circuit parameters.
Abstract: This paper investigates the optimal tradeoff between the degree of intermediate latching and cost in special-purpose VLSI chips, using the measure AP, where A is the chip area and P is the period (the reciprocal of throughput). The results show that significant reductions in AP-product (reciprocal of throughput per unit area) can be achieved by-intermediate latching in many typical signal processing applications, for a wide range of circuit parameters.
5 citations