Showing papers by "Kenneth Steiglitz published in 1985"

A note on 'free accumulation' in VLSI filter architectures

Abstract: Completely pipelined inner product architectures are presented for FIR filtering and linear transformation. The designs use only full adders, organized to form multipliers. By cascading these multiplier structures, no additional area or time is needed to sum their products. The merits of the FFT are briefly reconsidered in the context of high throughput VLSI structures for digital signal processing.

A multi-processor cellular automaton chip

Abstract: We describe the design and testing of an 18- processor chip that implements the update rule for a fixed one-dimensional binary-valued cellular automaton. The VLSI design was done in the high level, procedural language ALLENDE [5,6]. The processors are bit-serial, completely pipelined, and cascaded, so that one chip performs 18 updates per major clock cycle. In principle, any number of chips can be cascaded, with a corresponding linear speedup. Sixteen chips were fabricated in 4 µ nMOS using the MOSIS facility, of which 10 were fully functional. When tested, 9 of the fully functional chips operated at maximum clock rates between 6 and 8 Mhz. This implies a maximum speed of about 108bit updates per second per chip, and opens the way for experimentation that is too time-consuming using general purpose devices.

Time-power-area tradeoffs for the nMOS VLSI full-adder

Abstract: We study the problem of optimizing the pulldown diffusion widths in the one-bit full adder when it is embedded in a regular array, using the simplest possible array multiplier with a delay-time criterion as an example. A local optimization algorithm is used, which varies two parameters at a time along the critical path until a local optimum is found. The analysis routines include the Berkeley tools [10] and the Princeton procedural layout language ALLENDE [11- 12]. Two ways are suggested for optimizing large arrays in practical amounts of time. First, the full-adder cell optimized within a minimum-size array can be used in the large array. This is a good choice because the interior cells of the small prototype have the same boundary conditions as those in the larger array. A second, even faster, method is to approximate the delay time from some simple assumptions about the critical path. Numerical results show that both these methods are effective. We give typical local optima obtained when delay time is minimized, together with power-time tradeoff curves, for the 3×3 and 4×4 array multipliers, using 4µ (λ=2µ) nMOS fabrication parameters, and a 5- parameter random-logic full-adder cell.

Hierarchical, Parallel and Systolic Array Processing

Abstract: Many signal processing algorithms are highly regular, data-independent, and access the data in fixed patterns. For these reasons the current technological advances in very large scale integrated circuits hold especially great promise for signal processing, and in fact we now see the development of many highly integrated processors of a more or less specialized nature. At one end of the spectrum, we see programmable signal processing chips that are really microprocessors, with program, memory and logic separated as in a general purpose machine. At the other extreme, we see highly-specialized, custom chips that perform fixed tasks; typically the data moves through the chip along fixed, regular paths, the arithmetic logic is distributed in space, and the “program” is really “hard-wired” into the topology. This talk is devoted to a study of this latter, custom variety of architecture.