Showing papers by "Kenneth Steiglitz published in 1986"
TL;DR: It is suggested that any analog computer can be simulated efficiently (in polynomial time) by a digital computer from the assumption that P ≠ NP and from this assumption the operation of physical devices used for computation is drawn.
188 citations
TL;DR: It is shown that as a class the FA's are equivalent to CA's, in the sense that the same array of space-generation values can be produced; they must be generated in a different order, however.
144 citations
TL;DR: In circumstances outlined here, hybrid analog-digital systems can be built which give the accuracy of digital solutions with intermediate degrees of speed and simplicity.
Abstract: Analog optical solutions of numerical problems tend to be fast, simple, and inaccurate. Digital optical or electronic solutions to the same problems tend to be slower, harder, and more accurate. In circumstances outlined here, hybrid analog-digital systems can be built which give the accuracy of digital solutions with intermediate degrees of speed and simplicity. Because at any instant these processors are working in either the analog or the digital mode, we call them bimodal optical computers.
36 citations
TL;DR: It is proved that some small array of one-bit full adders, called the canonical configuration, has the same local optima as the n × n multiplier for large n, with the criterion of minimizing the delay time T.
Abstract: We study the problem of optimizing the transistor sizes in the one-bit nMOS full adder either isolated or embedded in a regular array. A local optimization method that we call the critical-path optimization method is developed. In this method, two parameters at a time are changed along the critical path until a locally optimal choice of transistor sizes is found. The critical-path optimization method uses the Berkeley VLSI tools and the hierarchical layout language ALLENDE developed at Princeton. First, we optimize the isolated one-bit full adder implemented in three ways: as a PLA, data selector, and with random logic. The details of the critical-path optimization method and power-time tradeoff curves are illustrated here. Second, we optimize the one-bit full adder embedded in a simple array multiplier. The entire 3 × 3, 4 × 4, 8 × 8, and 10 × 10 multipliers are optimized and their local optima are compared. Because the optimization of the entire circuit becomes less practical when the circuit becomes larger, we develop a method that makes use of circuit regularity. We prove that some small array of one-bit full adders, called the canonical configuration, has the same local optima as the n × n multiplier for large n, with the criterion of minimizing the delay time T. Hence, we can greatly reduce the computation load by optimizing this canonical configuration instead of optimizing the entire circuit. Experimental results confirm the effectiveness of this approach.
15 citations