K
Kerim Kalafala
Researcher at IBM
Publications - 69
Citations - 1721
Kerim Kalafala is an academic researcher from IBM. The author has contributed to research in topics: Static timing analysis & Statistical static timing analysis. The author has an hindex of 13, co-authored 68 publications receiving 1700 citations.
Papers
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Proceedings ArticleDOI
First-order incremental block-based statistical timing analysis
TL;DR: In this article, a canonical first order delay model is proposed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form and the sensitivities of all timing quantities to each of the sources of variation are available.
Journal ArticleDOI
First-Order Incremental Block-Based Statistical Timing Analysis
Chandu Visweswariah,Kaushik Ravindran,Kerim Kalafala,Steven G. Walker,Sambasivan Narayan,D.K. Beece,Jeffrey S. Piaget,Natesan Venkateswaran,Jeffrey G. Hemmett +8 more
TL;DR: A canonical first-order delay model that takes into account both correlated and independent randomness is proposed, and the first incremental statistical timer in the literature is reported, suitable for use in the inner loop of physical synthesis or other optimization programs.
Proceedings ArticleDOI
Statistical timing for parametric yield prediction of digital integrated circuits
TL;DR: Three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits are proposed and results in the face of statistical temperature and Vdd variations are presented.
Patent
System and method for correlated process pessimism removal for static timing analysis
TL;DR: In this article, a method of removing pessimism in static timing analysis is described, where delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account.
Journal ArticleDOI
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits
TL;DR: Three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits are proposed and results in the face of statistical temperature and Vdd variations are presented.