Ketan Shringarpure

Bio: Ketan Shringarpure is an academic researcher from Missouri University of Science and Technology. The author has contributed to research in topics: Power integrity & Printed circuit board. The author has an hindex of 9, co-authored 21 publications receiving 203 citations. Previous affiliations of Ketan Shringarpure include Apple Inc. & University of Missouri.

Equivalent Circuit Model for Power Bus Design in Multi-Layer PCBs With Via Arrays

Abstract: An equivalent circuit model for multilayer power planes with multiple via arrays is proposed. The complexity of the actual geometry is greatly reduced in the circuit model with the accuracy maintained. The model is corroborated by measurements.

Analytical expressions for transfer function of supply voltage fluctuation to jitter at a single-ended buffer

Abstract: In this paper, the transfer function of a supply voltage fluctuation to jitter is analytically solved for a single ended buffer in closed-form expressions. The expressions for the jitter transfer function is validated by comparison with HSPICE simulation, and applied to an example for statistical jitter estimation.

Formulation and Network Model Reduction for Analysis of the Power Distribution Network in a Production-Level Multilayered Printed Circuit Board

Abstract: A methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented. The proposed model is based on inductance extraction from first principle formulation of a cavity formed by parallel metal planes. Circuit reduction is used to practically realize the model for a production level, complex, multilayer PCBs. The lumped element model is compatible with SPICE-type simulators. The resulting model has a relatively simple circuit topology. The model is corroborated with microprobing measurements up to a few gigahertz. The model can be used for a wide range of geometry variations in a power integrity analysis, including complex power/ground stack up, various numbers of decoupling capacitors with arbitrary locations, numerous IC power pins and IC power/ground return via layouts, as well as hundreds of ground return vias.

Plane-Pair PEEC Model for Power Distribution Networks With Sub-Meshing Techniques

Abstract: We present an improved plane-pair partial element equivalent circuit (PEEC) model for power distribution network modeling based on the PEEC formulation. The model can include via connections, decoupling capacitor macro-models, and discontinuities such as holes in the plane-pairs. An efficient approximate inductance sub-meshing model is described for large printed circuit plane-pairs with complex geometries and numerous vias. The modified nodal analysis (MNA) used leads to a flexible circuit solution where we can compute inductances, resistances, impedances, or other circuit models, including dc solutions. The MNA equations include effective optimizations such as the placement of capacitors. Today, a large class of methods are available based on numerous formulations including finite-difference time-domain, finite-element method, integral equation model, and cavity models. Each of the approaches has its own type of problems for which it is most suitable.

Characterization of PCB Dielectric Properties Using Two Striplines on the Same Board

Abstract: Signal integrity (SI) and power integrity (PI) modelling and design require accurate knowledge of dielectric properties of printed circuit board (PCB) laminate dielectrics. Dielectric properties of a laminate dielectric can be obtained from a set of the measured S-parameters on a PCB stripline with a specially designed through-reflect-line (TRL) calibration pattern. In this work, it is proposed to extract dielectric properties from the measurements of S-parameters on the two 50-Ohm stripline structures of the same length, but different widths of the trace, designed on the same layer of a PCB. The dielectric properties on these two lines should be identical. However, an application of the simplest "root-omega" technique to extract dielectric properties of the substrate would lead to the ambiguity in the extracted data. This is because the conductor surface roughness affects the measured S-parameters and is lumped in the extracted dielectric data. This problem of ambiguity in the dielectric properties extraction can be overcome using the approach analogous to the recently proposed method to separate dielectric and conductor losses on PCB lines with different widths and roughness profiles (1).

A Review on Power Supply Induced Jitter

Abstract: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.

Analytical Transfer Functions Relating Power and Ground Voltage Fluctuations to Jitter at a Single-Ended Full-Swing Buffer

Abstract: The transfer functions relating supply voltage fluctuations to jitter are analytically derived in closed form expressions for a single-ended buffer. The analytic transfer functions are derived from a linear differential equation obtained from asymptotic linear inverter I-V curves. The transfer functions are validated by comparison with HSPICE simulations. The estimated jitter is compared with the simulated jitter using eye diagrams with single-frequency and multitone supply voltage fluctuations.

Propagation Delay-Based Expression of Power Supply-Induced Jitter Sensitivity for CMOS Buffer Chain

Abstract: This paper demonstrates a very simple and highly accurate expression of power supply-induced jitter sensitivity transfer function for CMOS buffer chain. The transfer function is mainly a function of the maximum and minimum propagation delay of the buffer chain. The function can be easily obtained and used in jitter budget calculation.

Analytical Probability Density Calculation for Step Pulse Response of a Single-Ended Buffer With Arbitrary Power-Supply Voltage Fluctuations

Abstract: An analytical methodology to calculate the probability density functions (PDFs) for the step pulse response of a single-ended buffer with arbitrary power-supply voltage fluctuations is proposed. To validate the theory, a silicon IC with noise-aggressing buffers and a victim buffer was designed, fabricated, and assembled in a printed circuit board (PCB). The overall power distribution network (PDN) of the IC and PCB was modeled from impedance measurements. The PDFs of the step pulse response of the victim buffer with power-supply voltage fluctuations were calculated and validated by comparisons with HSPICE and experimental results. The obtained PDFs due to power-supply voltage fluctuations could be combined with the statistical link simulation methods for quick estimation of bit error rate (BER).