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Author

Keunwoo Kim

Other affiliations: DARPA, Samsung, National Ilan University  ...read more
Bio: Keunwoo Kim is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Static random-access memory. The author has an hindex of 22, co-authored 115 publications receiving 1965 citations. Previous affiliations of Keunwoo Kim include DARPA & Samsung.


Papers
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Journal ArticleDOI
TL;DR: For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.
Abstract: Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experimental progress in just a few years. Fully integrated CMOS circuits have been demonstrated in a 180 nm foundry-compatible process, and methods for mapping conventional, planar CMOS product designs to FinFET have been developed. For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.

413 citations

Journal ArticleDOI
TL;DR: In this article, the random-dopant-fluctuation (RDF) effects in FinFET devices are investigated via physical analyses and numerical simulations. And the implication from RDF for design is also discussed.
Abstract: In this brief, the random-dopant-fluctuation (RDF) effects in FinFET devices are investigated via physical analyses and numerical simulations. Our results show that extremely scaled devices, particularly FinFETs with narrow device width (fin height) in each individual fin, are susceptible to RDF effects. Even in an ideally ldquoundopedrdquo silicon channel, the existence of unintended impurity dopants of acceptors and donors will still have a significant impact on device characteristics. The implication from RDF for design is also discussed.

128 citations

Journal ArticleDOI
TL;DR: In this paper, the thresholdvoltage difference between doublegated and single-gated modes in a high-VT DG device is exploited to reduce the number of transistors required to implement stack logic.
Abstract: Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations

93 citations

Patent
12 Apr 2006
TL;DR: In this paper, the back gate bias voltage is dynamically controlled on pull-up pFETs in a FinFET SRAM cell, based on an operational mode (e.g., Read, Half-Select, Write, Standby).
Abstract: The present invention provides dynamic control of back gate bias on pull-up pFETs in a FinFET SRAM cell. A method according to the present invention includes providing a bias voltage to a back gate of at least one transistor in the SRAM cell, and dynamically controlling the bias voltage based on an operational mode (e.g., Read, Half-Select, Write, Standby) of the SRAM cell.

70 citations

Patent
07 Apr 2005
TL;DR: In this paper, an eight transistor static random access memory (SRAM) device, comprising first and second inverters, a first bit line, first complement bit line and a pair of read access transistors, was described.
Abstract: Disclosed is an eight transistor static random access memory (SRAM) device, comprising first and second inverters, a first bit line, a first complement bit line, a pair of write access transistors, and a pair of read access transistors. Each of the first and second inverters includes a respective pair of transistors, and has a respective data node. Each of a first and a second of the access transistors has a source, a drain, a front gate, and a back gate. The first access transistor is coupled to the first bit line, and the second access transistor is coupled to the first complement bit line. The back gate of the first access transistor is coupled to the data node of the first inverter; and the back gate of the second access transistor is coupled to the data node of the second inverter. This increases the difference between the threshold voltages of the first and second access transistors.

66 citations


Cited by
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Journal ArticleDOI
20 Apr 2010
TL;DR: The physics behind this large resistivity contrast between the amorphous and crystalline states in phase change materials is presented and how it is being exploited to create high density PCM is described.
Abstract: In this paper, recent progress of phase change memory (PCM) is reviewed. The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. The scaling properties of PCM are illustrated with recent experimental results using special device test structures and novel material synthesis. Factors affecting the reliability of PCM are discussed.

1,488 citations

Patent
27 Nov 2008
TL;DR: In this paper, recent progress of phase change memory (PCM) is reviewed and innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3D, multilayer high-density memory arrays are described.
Abstract: A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact.

936 citations

Journal ArticleDOI
17 Nov 2011-Nature
TL;DR: In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue.
Abstract: For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

842 citations

Journal ArticleDOI
01 Nov 2010
TL;DR: In this article, a junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices using bulk conduction instead of surface channel.
Abstract: Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.

458 citations