Klaas Bult

Bio: Klaas Bult is an academic researcher from Broadcom. The author has contributed to research in topics: CMOS & Amplifier. The author has an hindex of 21, co-authored 52 publications receiving 2207 citations. Previous affiliations of Klaas Bult include Bosch & Delft University of Technology.

A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2/

Abstract: A 10-b current steering CMOS digital-to-analog converter (DAC) is described, with optimized performance for frequency domain applications. For sampling frequencies up to 200 MSample/s, the spurious free dynamic range (SFDR) is better than 60 dB for signals from DC to Nyquist. For sampling frequencies up to 400 MSample/s, the SFDR is better than 55 dB for signals from DC to Nyquist. The measured differential nonlinearity and integral nonlinearity are 0.1 least significant bit (LSB) and 0.2 LSB, respectively. The circuit is fabricated in a 0.35-/spl mu/m, single-poly, four-metal, 3.3 V, standard digital CMOS process and occupies 0.6 mm/sup 2/. When operating at 500 MSample/s, it dissipates 125 mW from a 3.3 V power supply. This DAC is optimized for embedded applications with large amounts of digital circuitry.

An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm/sup 2/

Abstract: A distributed-gain preamplifier uses averaging to improve resolution by 4 b in differential nonlinearity (DNL) and 2 b in integral nonlinearity (INL) in a flash analog-to-digital converter (ADC). Fabricated in a 0.5-/spl mu/m, triple-metal, single-poly CMOS process, the circuit measures 1.4 mm/spl times/1.4 mm including a bandgap and a sample-and-hold (SH), while the ADC itself occupies 1-mm/sup 2/. At a conversion rate of 50-MS/s the ADC dissipates 170 mW, the SH dissipates 70 mW, and the untrimmed ADC-plus-SH exhibits 54 dB S/(N+D) with a 12-MHz 90% full-scale input.

Variable gain amplifier for low voltage applications

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

A 12 bit 2.9 GS/s DAC With IM3 $ ≪ -$ 60 dBc Beyond 1 GHz in 65 nm CMOS

Abstract: A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 < ?-60 dBc beyond 1 GHz while driving a 50 ? load with an output swing of 2.5 Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9n GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with ?always-ON? biasing.

Analog design in deep sub-micron CMOS

Abstract: Analog design in deep sub-micron technologies is a reality now and poses severe challenges to the circuit designer. Trends in technologies as well as circuit design are discussed. It is shown that the power required for a certain dynamic range and bandwidth decreases with minimum feature size as long as a constant ratio between signal swing and supply voltage can be maintained. Below 0.1µm channel-length, predictions of the threshold voltage endanger that requirement however. At circuit level, the problem that a low supply voltage poses on the use of switches and amplifiers is discussed. Various techniques are discussed to overcome these problems, like the use of low V th transistors, clock boosting, switched OpAmp technique, rail-to-rail input stages, back-gate driving circuits and CM level-shift techniques. Based on power estimates, the necessity of matching enhancing techniques like Auto-Zero techniques and Averaging is shown.

Hierarchical Data Collection Network Supporting Packetized Voice Communications Among Wireless Terminals and Telephones

Abstract: A packet-based, hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting substantially different characteristics are employed in an overall scheme to link portable or mobile computing devices. The network accommodates real time voice transmission both through dedicated, scheduled bandwidth and through a packet-based routing within the confines and constraints of a data network. Conversion and call processing circuitry is also disclosed which enables access devices and personal computers to adapt voice information between analog voice stream and digital voice packet formats as proves necessary. Routing pathways include wireless spanning tree networks, wide area networks, telephone switching networks, internet, etc., in a manner virtually transparent to the user. A voice session and associate call setup simulates that of conventional telephone switching network, providing well-understood functionality common to any mobile, remote or stationary terminal, phone, computer, etc.

Device mismatch and tradeoffs in the design of analog circuits

Abstract: Random device mismatch plays an important role in the design of accurate analog circuits. Models for the matching of MOS and bipolar devices from open literature show that matching improves with increasing device area. As a result, accuracy requirements impose a minimal device area and this paper explores the impact of this constraint on the performance of general analog circuits. It results in a fixed bandwidth-accuracy-power tradeoff which is set by technology constants. This tradeoff is independent of bias point for bipolar circuits whereas for MOS circuits some bias point optimizations are possible. The performance limitations imposed by matching are compared to the limits imposed by thermal noise. For MOS circuits the power constraints due to matching are several orders of magnitude higher than for thermal noise. For the bipolar case the constraints due to noise and matching are of comparable order of magnitude. The impact of technology scaling on the conclusions of this work are briefly explored.

0.5-V analog circuit techniques and their application in OTA and filter design

Abstract: We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.

Analog circuits in ultra-deep-submicron CMOS

Abstract: Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.