Koh Yamanaga

Bio: Koh Yamanaga is an academic researcher from Murata Manufacturing. The author has contributed to research in topics: Capacitor & Electrical impedance. The author has an hindex of 3, co-authored 13 publications receiving 32 citations. Previous affiliations of Koh Yamanaga include Tokyo Institute of Technology.

S-Parameter-Based Modal Decomposition of Multiconductor Transmission Lines and Its Application to De-Embedding

Abstract: Theory and experiments are presented of modal decomposition of scattering matrices of multiconductor transmission lines (TLs). In effect, n coupled TLs are decomposed into n independent ones. Its use is demonstrated by applying it to thru-only de-embedding of 4 coupled TLs (synthesized data) and 2 coupled TLs (measurement data from a 0.18 ?m-CMOS chip). The proposed de-embedding method could greatly facilitate accurate characterization of on-chip multiport networks.

Acceleration of random-walk-based linear circuit analysis using importance sampling

Abstract: This paper proposes an importance sampling (IS) technique based on quasi-zero-variance estimation for accelerating convergence of random-walk-based power grid analysis. In our approach, the alternative probability for IS is incrementally updated after every Mr samples of random walk so that more recent and thus more accurate node voltages are utilized to asymptotically achieve ideal zero-variance estimation. We also propose a method to determine efficient Mr for the r-th probability update; although smaller Mr results more aggressive update of alternative probability, the alternative probability becomes inaccurate if Mr is too small. The estimation error of the proposed method decreases O((M/r)-r/2), which breaks O(M-1/2), the slow convergence-rate barrier of normal Monte Carlo analysis. Our trial implementation achieved 790x speedup compared with a conventional random-walk-based circuit analysis for analyzing IBM power grid benchmark circuits at 1mV accuracy.

On-chip differential and common mode voltage measurement using off-chip referenced twin probing

Abstract: Direct measurement technique called off-chip referenced twin probing is presented. Both signal and ground lines are measured symmetrically using a pair of probes with built-in on-chip series resistors to minimize and predict probing invasiveness. Compensation procedure of the frequency dependence due to non-ideality of the probing system is defined to improve measurement fidelity in high-frequencies. In addition, by fully utilizing information from a pair of measurement waveform, on-chip common mode voltage is measured for the first time. Example measurement of a transmission line structure demonstrates 2 mV noise floor, -26 dB invasiveness, and more than 10 GHz bandwidth.

Substrate-geometry aware 2-port modeling for surface-mount passive components

Abstract: Electrical modeling methodology for surface-mount passive components is proposed. In order to accurately capture parasitic inductance, the proposed 2-port model accounts for surrounding ground layer configurations of the print circuit board (PCB) on which the component is mounted. Our model retains conventional modeling paradigm in which component suppliers provide their customers with simulation models characterized independently of the customerspsila PCB. We also present necessary corrections that compensate missing magnetic coupling between the models. Impedance of a power distribution network is experimentally analyzed being non-separated modeling as the reference. The proposed model achieved very good match with the reference result reducing 10-30% error of the conventional model to within 1%.

Accurate parasitic inductance determination of a ceramic capacitor through 2-port measurements

Abstract: Series and shunt measurement configurations for accurate determination of parasitic inductance of a ceramic capacitor are proposed. With the proposed measurement, longitudinal partial inductance along the capacitor is selectively extracted. Inductances perpendicular to the capacitor are carefully eliminated so that the component contribution to the magnetic field is exactly accounted for. In order to correctly represent inductance change due to the ground position, the proposed model inductance includes the effect of insulator layer thickness of the mounted printed circuit board. The inductances of series and the shunt measurements match very well, confirming that both methods extract correct parasitic inductance. Experimental analysis of a power distribution network inductance using the extracted model parameters achieved within 2% match with the measurement result.

Power distribution system design methodology and capacitor selection for modern CMOS technology

Abstract: Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients.

On the validity of bisection-based thru-only de-embedding

Abstract: The validity of the thru-only de-embedding method that uses mathematically bisected halves of a left-right symmetric THRU pattern is assessed in this paper. The popularly used T-equivalent representation of a THRU and the bisection thereof is neither unique nor its validity firmly established. It is shown that an equally simple T-equivalent-based bisection gives better results than the T-equivalent-based bisection by comparing the two bisecting methods with a result obtained from an independent method. The thru-only de-embedding method is also compared with the conventional open-short and short-open methods, and the interrelationship among them expected from the assumed equivalent circuit representations of the relevant dummy patterns is confirmed. This is made possible by using the odd-mode responses of symmetric 4-port devices as the 2-ports under study. This way, nonidealities associated with ordinary 2-port dummy patterns is avoided.

Differential wideband interconnects for organic millimeter wave chip packages: An effort to design an all-purpose RF chip package

Abstract: In this paper a chip package is presented that is optimized for high operation frequencies and high power applications with a moderate number of signal paths. Using standard printed circuit board (PCB) materials, the package is also very cost effective. For radio frequency (RF) applications, the connection between chip and package is as important as the connection between package and baseboard. This paper presents both and shows that the package-baseboard transition is dominating the insertion and return loss at frequencies above 40 GHz, when using organic PCBs as base for the packages. Moreover, some methods are introduced to simplify the simulation models of organic PCB transitions. Because of the fully impedance controlled design process, the presented transitions can be used from DC to 67 GHz and ensure best signal integrity.

Accurate Transistor Modeling by Three-Parameter Pad Model for Millimeter-Wave CMOS Circuit Design

Abstract: This paper proposes accurate CMOS device de-embedding and modeling methods. For millimeter-wave circuit design, accurate simulation models are required. For this reason, an accurate measurement is a key technique for device characterization, and de-embedding and modeling methods are also very important. In this work, a three-parameter pad model based on L-2L de-embedding method and a transistor model with frequency and bias dependency are proposed. The pad model is derived from the assumption that the capacitance of PADs becomes constant at high frequencies. In the transistor modeling, parasitic elements are extracted mathematically. A five-stage low-noise amplifier is fabricated by 65–nm CMOS technology to confirm the accuracy of simulation, and the simulation and measurement results match well with each other.

Mutual Inductance of Capacitor Low-Pass Filters

Abstract: This paper describes the magnetic coupling of simple SMD capacitor low-pass filters which is investigated by the method of partial elements (PEEC). Based on analytical equations, the improvement of simple filter structures is possible with the help of the PCB layout only. As has been shown by measurement and simulation, the advanced usage of one and two capacitors allows improvements of up to 20dB at 1 GHz resulting exclusively from the chosen PCB layout. Moreover, attenuation can be increased up to 42dB with low-ESL capacitors.