There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

An overview of the self-organizing map algorithm, on which the papers in this issue are based, is presented in this article.

The Self-Organizing Map

We present an overview of negative bias temperature instability (NBTI) commonly observed in p-channel metal–oxide–semiconductor field-effect transistors when stressed with negative gate voltages at elevated temperatures. We discuss the results of such stress on device and circuit performance and review interface traps and oxide charges, their origin, present understanding, and changes due to NBTI. Next we discuss the effects of varying parameters (hydrogen, deuterium, nitrogen, nitride, water, fluorine, boron, gate material, holes, temperature, electric field, and gate length) on NBTI. We conclude with the present understanding of NBTI and its minimization.

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

Substrate Processing Apparatus

The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.

· Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
· Views of FPGA programming beyond Verilog/VHDL
· Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

A high-efficiency CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. A differential-drive active gate bias mechanism simultaneously enables both low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency (PCE), especially under small RF input power conditions. A test circuit of the proposed differential-drive rectifier was fabricated with 0.18 mu m CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on the input RF signal frequency, output loading conditions and transistor sizing was also evaluated. At the single-stage configuration, 67.5% of PCE was achieved under conditions of 953 MHz, - 12.5 dBm RF input and 10 KOmega output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance. In addition, experimental results show the existence of an optimum transistor size in accordance with the output loading conditions. The multi-stage configuration for larger output DC voltage is also presented.

High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs

High efficiency CMOS rectifier circuit for UHF RFID applications has been developed The rectifier utilizes self Vth cancellation (SVC) scheme in which threshold voltage of MOSFETs is cancelled by applying gate bias voltage generated by output voltage of the rectifier itself Very simple circuit configuration and no power dissipation feature of the scheme enable excellent power conversion efficiency (PCE) especially in small RF input power conditions At higher RF input power conditions, PCE of the rectifier automatically decreases This is the built-in self-power-regulation function Proposed SVC CMOS rectifier has been fabricated with 035 mum CMOS process and the measured performance has been compared with other types of rectifiers The SVC CMOS rectifier achieves 29% PCE at -99 dBm RF input power condition This PCE is larger than ever reported rectifiers under the condition

High efficiency CMOS rectifier circuit with self-Vth-cancellation and power regulation functions for UHF RFIDs

The effect of the Si-SiO/sub 2/ interface microroughness on the electron channel mobility of n-MOSFETs was investigated The surface microroughness was controlled by changing the mixing ratio of NH/sub 4/OH in the NH/sub 4/OH-H/sub 2/O/sub 2/-H/sub 2/O solution in the RCA cleaning procedure The gate oxide was etched, following the evaluation of the electrical characteristics of MOS transistors, to measure the microroughness of the Si-SiO/sub 2/ interface with scanning tunneling microscopy (STM) As the interface microroughness increases, the electron channel mobility, which can be obtained from the current-voltage characteristics of the MOSFET, gets lower The channel mobility is around 360 cm/sup 2//V-s when the average interface microroughness is 02 nm, where the substrate impurity concentration is 45*10/sup 17/ cm/sup -3/, ie the electron bulk mobility is 400 cm/sup 2//V-s It goes down to 100 cm/sup 2//V-s when the interface microroughness exceeds 1 nm >

Dependence of electron channel mobility on Si-SiO/sub 2/ interface microroughness

Using a multiple-input high-functionality transistor neuron MOSFET (/spl nu/MOS), demonstrates a dramatic simplification of logic circuit configuration compared to conventional CMOS circuitry. The purpose of this paper is to present a new clocked /spl nu/MOS logic circuit scheme in which a clock-driven switching transistor attached to the floating gate is used not only to initialize the floating-gate charge but also to perform auto-adjusting of its inverting threshold that cancels the fluctuations arising from fabrication.

Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment

A high efficiency differential CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. Differential-drive topology enables simultaneous low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency(PCE), especially under small RF input power conditions. The differential-drive rectifier was fabricated with 0.18-mum CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on an input RF signal frequency and output loading conditions was also evaluated. 66% of PCE was achieved under conditions of 953 MHz, -12 dBm RF input and 10 KOmega DC output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance.

Koji Kotani

Papers

High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs

High efficiency CMOS rectifier circuit with self-Vth-cancellation and power regulation functions for UHF RFIDs

Dependence of electron channel mobility on Si-SiO/sub 2/ interface microroughness

Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment

Differential-drive CMOS rectifier for UHF RFIDs with 66% PCE at −12 dBm Input