Koji Sadamatsu

Bio: Koji Sadamatsu is an academic researcher from Mitsubishi Electric. The author has contributed to research in topics: Diode & Schottky barrier. The author has an hindex of 5, co-authored 10 publications receiving 119 citations.

6.5 kV schottky-barrier-diode-embedded SiC-MOSFET for compact full-unipolar module

Abstract: For higher-voltage SiC modules, larger SBD chips are required as free-wheel diodes to suppress current conduction of the body diodes of MOSFETs, which causes bipolar degradation following the expansion of stacking faults. By embedding an SBD into each unit cell of a 6.5 kV SiC-MOSFET, we achieved, without using external SBDs, a high-voltage switching device that is free from bipolar degradation. Expansion of the active area by embedding SBDs is only 10% or less, whereas the active area of external SBDs can be over three times larger than that of the coupled MOSFET. The fabricated 6.5 kV SBD-embedded SiC-MOSFETs show sufficiently high breakdown voltages, low specific on-resistances, no bipolar degradation, and good reliability.

Demonstration of SiC-MOSFET embedding Schottky barrier diode for inactivation of parasitic body diode

Abstract: External Schottky barrier diodes (SBD) are generally used to suppress the conduction of the body diode of MOSFET. A large external SBD is required for a high voltage module because of its high specific resistance, while the forward voltage of SBD should be kept smaller than the built-in potential of the body diode. Embedding SBD into MOSFET with short cycle length increases maximum source-drain voltage where body diode remains inactive, resulting in high current density of SBD current. We propose a MOSFET structure where an SBD is embedded into each unit cell and an additional doping is applied, which allows high current density in reverse operation without any activation of body diode. The proposed MOSFET was successfully fabricated and much higher reverse current density was demonstrated compared to the external SBD. We can expect to reduce total chip size of high voltage modules using the proposed MOSFET embedding SBD.

Advanced RFC technology with new cathode structure of field limiting rings for High Voltage planar diode

Abstract: The edge of the active area and termination structure have a decisive influence on the recovery safety operating area (SOA) of High Voltage (HV) freewheeling diodes (FWDs). We have investigated the HV planar anode diode that breaks the triangle trade-off limitations between the overall loss, the reverse recovery softness and the recovery SOA. Our results show the destruction phenomena during the recovery operation for HV diodes originate in the local heating caused by high electric field and high current density at the end of the active area. Therefore, a newly developed HV diode based on the Relaxed Field of Cathode (RFC) technology achieves high total performance by adopting a new cathode structure of the field limiting rings region. The new diode offers low overall loss combined with a high recovery SOA and superior snap-off capability. The proposed new diode structure demonstrates a clear triangle trade-off breakthrough between the overall loss, the reverse softness and the recovery SOA of the HV diode.

Impact of Embedding Schottky Barrier Diodes into 3.3 kV and 6.5 kV SiC MOSFETs

Abstract: External Schottky barrier diodes (SBDs) used as free-wheel diodes should be larger in higher voltage devices to avoid bipolar degradation consequent on current conduction of body diodes in SiC MOSFETs. By embedding an external SBD into an SiC MOSFET, we achieved compact 3.3 kV and 6.5 kV SiC MOSFETs that are free from bipolar degradation. The active area of the 3.3 kV/6.5 kV samples is only about a half/quarter of the total active area of a conventional MOSFET and a coupled external SBD.

Wide Cell Pitch LPT(II)-CSTBT™(III) technology rating up to 6500 V for low loss

Abstract: In this paper, an advanced High Voltage (HV) IGBT technology, which is focused on low loss and is the ultimate device concept for HV IGBT, is presented. CSTBTTM technology utilizing “ULSI technology” and “Light Punch-Through (LPT) II technology” (i.e. narrow Wide Cell Pitch LPT(II)-CSTBT(III)) for the first time demonstrates breaking through the limitation of HV IGBT's characteristics with voltage ratings ranging from 2500 V up to 6500 V. The improved significant trade-off characteristic between on-state voltage (V CE (sat)) and turn-off loss (E OFF ) is achieved by means of a “narrow Wide Cell Pitch CSTBT(III) cell”. In addition, this device achieves a wide operating junction temperature (@218 ∼ 448K) and excellent short circuit behavior with the new cell and vertical designs. The LPT(II) concept is utilized for ensuring controllable IGBT characteristics and achieving a thin N− drift layer. Our results cover design of the Wide Cell Pitch LPT(II)-CSTBT(III) technology and demonstrate high total performance with a great improvement potential.

Modular Multilevel Converters: State of the Art and Future Progress

Abstract: Modular multilevel converters (MMCs) have paved the way for power electronics in very demanding application areas. While becoming the worldwide standard for high-voltage dc (HVDC), many other future applications are emerging. More and more, the functionality and cost of power electronics must be judged from a superordinate system view. Passive components "around" the converter, such as mechanical switchgear, fuses, overvoltage surge suppressors, and filters offer very low potential for future progress. With respect to protection, the scope must be widened from the semiconductors to the protection of the associated equipment (e.g., motors, drive trains, power net, and so on).

Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) Using a Single Ohmic/Schottky Process Scheme

Abstract: This letter reports a new 900 V 4H-SiC JBSFET containing an MOSFET with an integrated JBS diode in the center area of the chip. Both MOSFET and JBS diode structures utilize the same edge termination structure,which results in 30% reduction in SiC wafer area consumption in case of 10 A rating device. In order to form a Schottky contact for the JBS diode as well as ohmic contacts for n+ source and p+ body of the MOSFET,a simple metal process flow has been newly developed. It was found that Ni can simultaneously form ohmic contacts on n+ and p+ implanted regions while it remains a Schottky contact on the n-epitaxial drift layer when it is annealed at moderate temperature (900°C for 2 min). The proposed JBSFET was successfully fabricated using a nine-mask on 6-in 4H-SiC wafers.

6.5 kV schottky-barrier-diode-embedded SiC-MOSFET for compact full-unipolar module

Abstract: For higher-voltage SiC modules, larger SBD chips are required as free-wheel diodes to suppress current conduction of the body diodes of MOSFETs, which causes bipolar degradation following the expansion of stacking faults. By embedding an SBD into each unit cell of a 6.5 kV SiC-MOSFET, we achieved, without using external SBDs, a high-voltage switching device that is free from bipolar degradation. Expansion of the active area by embedding SBDs is only 10% or less, whereas the active area of external SBDs can be over three times larger than that of the coupled MOSFET. The fabricated 6.5 kV SBD-embedded SiC-MOSFETs show sufficiently high breakdown voltages, low specific on-resistances, no bipolar degradation, and good reliability.

High efficiency high reliability SiC MOSFET with monolithically integrated Schottky rectifier

Abstract: A junction barrier controlled Schottky rectifier integrated silicon carbide MOSFET (SiC JMOS) is proposed in this paper, which merged a double implanted MOSFET (DMOS) and junction barrier controlled Schottky diode (JBS) in a monolithic SiC device without any additional process and area penalty. JMOS device in this work exhibits a lower reverse conduction voltage drop than conventional SiC DMOS. There is a 47% improvement on V SD . There's also superior in dynamic performances such like lower reverse recovery charge (Qrr) and maximum reverse recovery current (IRMax) due to characteristics of unipolar devices. As a result, JMOS is 54% lower in Q rr and 40% lower in I RMax . The integrated JBS could also prevent the potential failure caused by the transformation of dislocation defects into stacking faults due to the recombination of injected minority carriers when parasitic body diode in SiC MOSFET was turned on. In this work, we make characteristics comparison and build a testing platform to verify the efficiency and reliability improvement of SiC JMOS from conventional SiC DMOS. The experiment result shows that we could gain better system performance and reliability with less cost and higher power density.

Body PiN diode inactivation with low on-resistance achieved by a 1.2 kV-class 4H-SiC SWITCH-MOS

Abstract: Integration of SBD into SiC-MOSFET is promising to solve body-PiN-diode related problems known such as forward degradation and reverse recovery loss Particularly in lower breakdown-voltage-class SBD-integrated MOSFET, cell pitch reduction has a greater impact on inactivating the body-PiN-diode Here, we developed a novel device called an SBD-wall-integrated trench MOSFET (SWITCH-MOS), in which small cell pitch of 5pm was realized by utilizing trench side walls both for SBD and MOS channel with buried p+ layer The fabricated 12 kV SWITCH-MOS successfully suppressed the forward degradation under extremely high current density condition with low switching loss, low specific on-resistance, and low leakage current