Kong-Pang Pun

Bio: Kong-Pang Pun is an academic researcher from The Chinese University of Hong Kong. The author has contributed to research in topics: CMOS & Delta-sigma modulation. The author has an hindex of 21, co-authored 182 publications receiving 1973 citations. Previous affiliations of Kong-Pang Pun include Columbia University & City University of Hong Kong.

An efficient MFCC extraction method in speech recognition

Abstract: This paper introduces a new algorithm of extracting MFCC for speech recognition. The new algorithm reduces the computation power by 53% compared to the conventional algorithm. Simulation results indicate the new algorithm has a recognition accuracy of 92.93%. There is only a 1.5% reduction in recognition accuracy compared to the conventional MFCC extraction algorithm, which has an accuracy of 94.43%. However, the number of logic gates required to implement the new algorithm is about half of the MFCC algorithm, which makes the new algorithm very efficient for hardware implementation.

A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC

Abstract: A 0.5-V third-order one-bit fully-differential continuous-time DeltaSigma modulator is presented. The presented modulator architecture uses true low-voltage design techniques, and does not require internal voltage boosting or low-threshold devices. A return-to-open architecture that enables the ultra-low-voltage realization of return-to-zero signaling for the feedback DAC is proposed. The ultra-low-voltage operation is further enabled by a body-input gate-clocked comparator, and body-input operational transconductance amplifiers for the active-RC loop filter. Fabricated on a 0.18-mum CMOS process, the modulator achieves a peak SNDR of 74 dB in a 25 kHz bandwidth, and occupies an area of 0.6 mm2; the modulator core consumes 300 muW.

High-performance CMOS current comparator

Abstract: A new high-performance CMOS current comparator is proposed. By adding two inverters in the feedback loop of Traff's comparator, the proposed comparator exhibits significant speed improvement especially for low input currents. Simulated in a 0.18 mum CMOS technology, the comparator achieves a 0.6 ns delay for a 100 nA input current at 1.8 V supply, which is about eight times faster than Traff's comparator.

Reversed nested Miller compensation with voltage buffer and nulling resistor

Abstract: This paper presents a new reversed nested Miller compensation technique for multistage operational amplifier (opamp) design. The new compensation technique inverts the sign of the right half complex plane zero and shifts the frequency of the complex conjugate poles to a higher frequency. Simulation results indicate that the gain-bandwidth product and settling time are improved by factors of two and three, respectively, without degrading stability and power consumption. To verify the proposed technique, a three-stage opamp is fabricated with 0.6-/spl mu/m CMOS technology. The measured results of the test circuit agree with the results that are obtained from theoretical analysis and circuit simulation.

Next-Generation Delta-Sigma Converters: Trends and Perspectives

Abstract: This paper presents an overview of emerging circuits and systems techniques which are at the forefront of the state of the art in $\Delta\Sigma$ modulators, pushing their performance forward and giving rise to new generations of data converters. Among others, those strategies involving the development of new applications and paradigms—like RF/GHz-range $\Delta\Sigma$ digitisation, digital-assisted embedded loop filters, time-to-digital conversion and hybrid $\Delta\Sigma$ /Nyquist-rate architectures—are discussed, as well as the implications and design challenges derived from their integration in deep nanometer CMOS technologies. The envisioned $\Delta\Sigma$ techniques are presented in a systematic way around the main analog building blocks embedded in a $\Delta\Sigma$ modulator, i.e., the loop filter and the quantizer. Analysing the trends in the design of these blocks allows us to offer perspectives on how $\Delta\Sigma$ converters will evolve in the next years.

The Perception of the Visual World. By James J. Gibson. U.S.A.: Houghton Mifflin Company, 1950 (George Allen & Unwin, Ltd., London). Price 35s.

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Design Of Analog Cmos Integrated Circuits

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Wireless Power Transfer—An Overview

Abstract: Due to limitations of low power density, high cost, heavy weight, etc., the development and application of battery-powered devices are facing with unprecedented technical challenges. As a novel pattern of energization, the wireless power transfer (WPT) offers a band new way to the energy acquisition for electric-driven devices, thus alleviating the over-dependence on the battery. This paper presents an overview of WPT techniques with emphasis on working mechanisms, technical challenges, metamaterials, and classical applications. Focusing on WPT systems, this paper elaborates on current major research topics and discusses about future development trends. This novel energy transmission mechanism shows significant meanings on the pervasive application of renewable energies in our daily life.

Circularity-Based I/Q Imbalance Compensation in Wideband Direct-Conversion Receivers

Abstract: Communication receivers that utilize I/Q downconversion are troubled by amplitude and phase mismatches between the analog I and Q branches. These mismatches are unavoidable in practice and reduce the obtainable image frequency attenuation to the 20-40-dB range in practical receivers. In wideband multichannel receivers, where the overall bandwidths are in the range of several megahertz and the incoming carriers located at each other's mirror frequencies have a high dynamic range, the image attenuation of the analog front-end (FE) alone is clearly insufficient. In this paper, two novel blind low-complexity I/Q imbalance compensation techniques are proposed and analyzed to digitally enhance the analog FE image attenuation in wideband direct-conversion receivers. The proposed algorithms are grounded on the concept of circular or proper complex random signals, and they are, by design, able to handle the often overlooked yet increasingly important case of frequency-dependent I/Q mismatches. The first technique is an iterative one, stemming from adaptive filtering principles, whereas the second one is a moment-estimation-based block method. The performance of the algorithms is evaluated through computer simulations, as well as real-world laboratory signal measurement examples in practical multicarrier receiver cases. Based on the obtained results, the proposed compensation techniques can provide very good compensation performance with low computational resources and are robust in the face of different imbalance levels and dynamics of the received signals, as well as many other crucial practical aspects such as the effects of the communications channel and carrier synchronization.