Kota Nakahira

Bio: Kota Nakahira is an academic researcher from Tohoku University. The author has contributed to research in topics: Residual stress & Stress (mechanics). The author has an hindex of 1, co-authored 4 publications receiving 6 citations.

Measurement of the local residual stress between fine metallic bumps in 3D flip chip structures

Abstract: The local thermal deformation of the chips mounted by area-arrayed fine bumps has increased drastically because of the decrease of the flexural rigidity of the thinned chips. In this paper, the dominant structural factors of the local residual stress in a silicon chip are investigated quantitatively based on the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 µm and a unit cell consisted of four gauges with different crystallographic directions. This alignment of strain gauges enables to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made by silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 µm and the bump pitch was varied from 400 µm to 1,000 µm. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps.

Minimization of the local residual stress in 3DICs by controlling the structures and mechanical properties of 3D interconnections

Abstract: Since the residual stress in a silicon chip mounted in 3D modules causes the degradation of both electrical and mechanical reliability, the dominant factors of the residual stress was investigated by using a finite element method and experiments applying 2-μm long piezoresistance strain gauges. The residual stress and local deformation of the chip were found to vary drastically depending on the mechanical properties of bumps and underfill and bump alignment structures.

the Change of the Residual Stress in N ano-scale Transistors During the Deposition and Fine Patterning Processes of Thin Films

Abstract: The embedded strain gauges in a PQC-TEG were applied to the measurement of the change of the residual stress in a transistor structure with a 50-nm wide gate during thin film processing. The change of the residual stress was successfully monitored through the process such as the deposition and etching of thin films. Tn addition, the fluctuation of the process such as the intrinsic stress of thin films and the height and the width of the etched structures was also detected by the statistical analysis of the measured data. The sensitivity of the measurement was 1 MPa and it was validated that the amplitude of the fluctuation exceeded 100 MPa. This technique is also effective for detecting the spatial distribution of the stress in a wafer and its fluctuation among wafers.

Evaluation of the change of the residual stress in nano-scale transistors during the deposition and fine patterning processes of thin films

Abstract: The embedded strain gauges in a PQC-TEG were applied to the measurement of the change of the residual stress in a transistor structure with a 50-nm wide gate during thin film processing. The change of the residual stress was successfully monitored through the process such as the deposition and etching of thin films. In addition, the fluctuation of the process such as the intrinsic stress of thin films and the height and the width of the etched structures was also detected by the statistical analysis of the measured data. The sensitivity of the measurement was 1 MPa and it was validated that the amplitude of the fluctuation exceeded 100 MPa. This technique is also effective for detecting the spatial distribution of the stress in a wafer and its fluctuation among wafers.

Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors

Abstract: Three-dimensional integrated circuit (3D IC) is one of the promising ways to enhance IC performance. Each IC chip is mechanically connected by organic adhesive and metal microbumps. Coefficient of thermal expansion (CTE) mismatch between materials causes local bending stress in IC chips, leading to negative effects in IC performance. In this study, we have fabricated a test structure with DRAM cell array having planar MOS capacitors. Using the test structure, we measured both DRAM chip bending profiles and retention time modulations of DRAM cell array. Consequently, we have successfully demonstrated that the local bending stress in IC chips can be two-dimensionally evaluated using the DRAM cell array with planar MOS capacitances. This evaluation methods leads to realization of 3D IC with high reliability.

Quantitative evaluation of orbital hybridization in carbon nanotubes under radial deformation using π-orbital axis vector

Abstract: When a radial strain is applied to a carbon nanotube (CNT), the increase in local curvature induces orbital hybridization. The effect of the curvature-induced orbital hybridization on the electronic properties of CNTs, however, has not been evaluated quantitatively. In this study, the strength of orbital hybridization in CNTs under homogeneous radial strain was evaluated quantitatively. Our analyses revealed the detailed procedure of the change in electronic structure of CNTs. In addition, the dihedral angle, the angle between π-orbital axis vectors of adjacent atoms, was found to effectively predict the strength of local orbital hybridization in deformed CNTs.

Cyclic electromechanical response of poly(vinylidene fluoride)

Abstract: In this study, we present the results of cyclic electromechanical experiments conducted on uniaxially stretched poly(vinylidene fluoride) (PVDF) films. The experiments were carried out over a range of applied displacement amplitude ranging from 0.5 mm to 1.5 mm, superposed on an initial stretch on the test samples. The strains were calculated using non-contact speckle monitoring method. The hysteresis plots of mechanical and electromechanical cyclic responses are presented. Stress relaxation was observed up to 70% in orthogonal to stretch direction and 16% in the stretch direction. Observed piezoelectricity along both the directions is reported and discussed in the paper.

Thermal stability of electroplated copper thin-film interconnections

Abstract: There were local distributions of the crystallinity and resistance in a test interconnection. The local resistance of the interconnection varied with the local crystallinity. The maximum temperature appeared in the local area with the minimum crystallinity, in other words, the area with the highest resistance under the application of high current density of 10 MA/cm2. Thus, local high Joule heating occurred in the test interconnection due to the local variation of the crystallinity of the interconnection. The maximum temperature decreased from about 170°C to 140°C when the average crystallinity (IQ value which was obtained from EBSD analysis) increased from 3000 to 4100. This decrease of the maximum temperature can be explained by the decrease of Joule heating under the application of a fixed current density. This decrease of the maximum temperature increased the long-term reliability of the interconnections drastically.

Evaluation of in-plane local stress distribution in stacked IC chip using dynamic random access memory cell array for highly reliable three-dimensional IC

Abstract: As three-dimensional (3D) ICs have many advantages, IC performances can be enhanced without scaling down of transistor size. However, 3D IC has mechanical stresses inside Si substrates owing to its 3D stacking structure, which induces negative effects on transistor performances such as carrier mobility changes. One of the mechanical stresses is local bending stress due to organic adhesive shrinkage among stacked IC chips. In this paper, we have proposed an evaluation method for in-plane local stress distribution in the stacked IC chips using retention time modulation of a dynamic random access memory (DRAM) cell array. We fabricated a test structure composed of a DRAM chip bonded on a Si interposer with dummy Cu/Sn microbumps. As a result, we clarified that the DRAM cell array can precisely evaluate the in-plane local stress distribution in the stacked IC chips.