Image sensors are used in all digital cameras, mobile phones and all other devices where images are to be captured. The most common parameter used by consumers to compare the different cameras is the pixel array size which is usually given in Mega pixels. The image quality is better with a higher megapixel count. Another parameter to distinguish between the different cameras is the type of imaging technology used like CMOS (Complementary metal oxide semiconductor) or CCD (Charge coupled devices). In this review we will present the working principles of an image sensor and conversion of light to electrical signals and subsequently to an image. The functional differences between the CCD and CMOS sensors will also be presented.

https://iopscience.iop.org/article/10.1088/1742-6596/1714/1/012055/pdf

A Review on Image Processing Sensor

The planet earth has been facing COVID-19 epidemic as a challenge in recent time. It is predictable that the world will be fighting the pandemic by taking precautions steps before an operative vaccine is found. The IoT produces huge data volumes, whether private or public, through the invention of IoT devices in the form of smart devices with an improved rate of IoT data generation. A lot of devices interact with each other in the IoT ecosystem through the cloud or servers. Various techniques have been presented in recent time, using data mining approach have proven help detect possible cases of coronaviruses. Therefore, this study uses machine learning technique (ABC and SVM) to predict COVID-19 for IoT data system. The system used two machine learning techniques which are Artificial Bee Colony algorithm with Support Vector Machine classifier on a San Francisco COVID-19 dataset. The system was evaluated using confusion matrix and had a 95% accuracy, 95% sensitivity, 95% specificity, 97% precision, 96% F1 score, 89% Matthews correlation coefficient for ABC-L-SVM and 97% accuracy, 95% sensitivity, 100% specificity, 100% precision, 97% F1 score, 93.1% Matthews correlation coefficient for ABC-Q-SVM. In conclusion, the system shows that the process of dimensionality reduction utilizing ABC feature extraction techniques can boost the classification production for SVM. It was observed that fetching relevant information from IoT systems before classification is relatively beneficial. 

/pdf/machine-learning-based-iot-system-for-covid-19-epidemics-25r7d4di.pdf

Machine learning-based IoT system for COVID-19 epidemics

Air pollution monitoring system using IoT devices: Review

In-memory computing using emerging technologies such as resistive random-access memory (ReRAM) addresses the ‘von Neumann bottleneck’ and strengthens the present research impetus to overcome the memory wall. While many methods have been recently proposed to implement Boolean logic in memory, the latency of arithmetic circuits (adders and consequently multipliers) implemented as a sequence of such Boolean operations increases greatly with bit-width. Existing in-memory multipliers require <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$O(n^{2})$ </tex-math></inline-formula> cycles which is inefficient both in terms of latency and energy. In this work, we tackle this exorbitant latency by adopting Wallace Tree multiplier architecture and optimizing the addition operation in each phase of the Wallace Tree. Majority logic primitive was used for addition since it is better than NAND/NOR/IMPLY primitives. Furthermore, high degree of gate-level parallelism is employed at the array level by executing multiple majority gates in the columns of the array. In this manner, an in-memory multiplier of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$O(n.log(n))$ </tex-math></inline-formula> latency is achieved which outperforms all reported in-memory multipliers. Furthermore, the proposed multiplier can be implemented in a regular transistor-accessed memory array without any major modifications to its peripheral circuitry and is also energy-efficient. 

/pdf/a-novel-in-memory-wallace-tree-multiplier-architecture-using-sylfoej4.pdf

A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

In this paper, the impact of dust deposition on solar photovoltaic (PV) panels was examined, using experimental and machine learning (ML) approaches for different sizes of dust pollutants. The experimental investigation was performed using five different sizes of dust pollutants with a deposition density of 33.48 g/m2 on the panel surface. It has been noted that the zero-resistance current of the PV panel is reduced by up to 49.01% due to the presence of small-size particles and 15.68% for large-size (ranging from 600 µ to 850 µ). In addition, a significant reduction of nearly 40% in sunlight penetration into the PV panel surface was observed due to the deposition of a smaller size of dust pollutants compared to the larger size. Subsequently, different ML regression models, namely support vector machine (SVMR), multiple linear (MLR) and Gaussian (GR), were considered and compared to predict the output power of solar PV panels under the varied size of dust deposition. The outcomes of the ML approach showed that the SVMR algorithms provide optimal performance with MAE, MSE and R2 values of 0.1589, 0.0328 and 0.9919, respectively; while GR had the worst performance. The predicted output power values are in good agreement with the experimental values, showing that the proposed ML approaches are suitable for predicting the output power in any harsh and dusty environment.

/pdf/quantitative-analysis-of-solar-photovoltaic-panel-2k3leux8.pdf

Quantitative Analysis of Solar Photovoltaic Panel Performance with Size-Varied Dust Pollutants Deposition Using Different Machine Learning Approaches

Major operation block in any processing unit is a multiplier. There are many multiplication algorithms are proposed, by using which multiplier structure can be designed. Among various multiplication algorithms, Wallace tree multiplication algorithm is beneficial in terms of speed of operation. With the advancement of technology, demand for circuits with high speed and low area is increasing. In order to improve the speed of Wallace tree multiplier without degrading its area parameter, a new structure of Wallace tree multiplier is proposed in this paper. In the proposed structure, the final addition stage of partial products is performed by parallel prefix adders (PPAs). In this paper, five Wallace tree multiplier structures are proposed using Kogge stone adder, Sklansky adder, Brent Kung adder, Ladner Fischer adder and Han carlson adder. All the multiplier structures are designed using Verilog HDL in Xilinix 13.2 design suite. The proposed structures are simulated using ISIM simulator and synthesized using XST synthesizer. The proposed designs are analyzed with respect to traditional multiplier design in terms of area (No. of LUTs) and delay (ns).

Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI circuit designs

IoT is one of the best among the emerging technologies Its scope has into the field of agriculture in which farmers learn to control his farm using IoT Due to the lack of continuous human effort and optimal climatic conditions, many crops go waste every year This paper discusses various methods that prevent manual action and added automatic control of the farm by using machine learning algorithms and IoT sensors For example, support vector machine (SVR) is the method to check the weather conditions in every interval of time and gives data to the farmer and automatically takes the respective action To detect the pests, image processing is the best-used technique For controlling pests, we use pesticides spray by Drones and agricultural robots This reduces costs, human effort and saves time Irrigation can also be controlled by using the k-means clustering algorithm Greenhouses are the best technique, which is being used nowadays in the precision agriculture that takes information about the growth of a particular plant and gives that information to the farmer It also checks the internal climatic conditions

Analysis of Precision Agriculture Technique by Using Machine Learning and IoT

Multipliers are mainly used in digital signal processing (DSP) applications. The multiplier is the most popular one out of all existing arithmetic operations. It is used to perform the multiplication between two numbers in different types of approaches. Mainly the multiplier focuses on the four aspects to form an efficient multiplier, i.e., speed, power consumption, area, and accuracy. In this article, it covers all existing popular multipliers like booth, array, Wallace tree, sequential, logarithm, and combinational multiplier. In addition to this, we discussed the modified booth multiplier and its properties. At last, we compared each multiplier w.r.t their performance parameters like speed, time delay, area, complexity, accuracy, and power consumption.

Review on Different Types of Multipliers and Its Performance Comparisons

Low energy- and area-efficient digital circuit design is unique among the significant navigational challenges of digital VLSI design suitable for real-time applications. Full adders are essential functional elements in complex arithmetic circuits; a 1-bit adder is developed by using adiabatic logic in this operation to get low power consumption. The intended 1-bit adder cell with adiabatic logic results in very less heat dissipation with its surrounding circuit atmosphere. As a result, this logic has minimal energy loss due to overheating dissipation. The proposed adiabatic logic circuit is compared with CMOS and pass transistor logic (PTL) with TG 1-bit adder topologies. The results show that there are significant advantages in power saving compared to CMOS and pass transistor cells. The proposed adiabatic logic full adder requires 18 transistors to design. The proposed adiabatic logic 1-bit adder, designed with three inputs, produces the output response as true and complementary outputs in a single architecture. All full adder cells were designed with 65 nm technology and compared area and power consumption.

Krishna Saladi

Papers

Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI circuit designs

Analysis of Precision Agriculture Technique by Using Machine Learning and IoT

Review on Different Types of Multipliers and Its Performance Comparisons

Adiabatic Logic-Based Area- and Energy-Efficient Full Adder Design