K
Kritika Aditya
Researcher at Indian Institute of Technology Delhi
Publications - 13
Citations - 96
Kritika Aditya is an academic researcher from Indian Institute of Technology Delhi. The author has contributed to research in topics: Silicon on insulator & Irradiation. The author has an hindex of 4, co-authored 13 publications receiving 51 citations. Previous affiliations of Kritika Aditya include Synopsys.
Papers
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Journal ArticleDOI
Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET
Ramendra Singh,Kritika Aditya,S. S. Parihar,Yogesh Singh Chauhan,Reinaldo A. Vega,Terence B. Hook,Abhisek Dixit +6 more
TL;DR: This letter investigates the RF performance of a negative capacitance FinFET using BSIM-CMG compact model extracted from DC and RF measured data of 10-nm technology node devices, and finds that NC-FinFET’s cut-off frequency is a function of LaTeX, and observes that the self-heating effect in NC-finFET increases with increase ininline-formula.
Journal ArticleDOI
Experimental Evaluation of Self-Heating and Analog/RF FOM in GAA-Nanowire FETs
TL;DR: The characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz shows a good correlation with the measurement data and the self-heating effect (SHE) is significant in short-channel silicon on insulator (SOI) NWFets.
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A Junctionless Accumulation Mode NC-FinFET Gate Underlap Design for Improved Stability and Self-Heating Reduction
TL;DR: In this article, a metal ferroelectric insulator semiconductor (MFIS) -type junctionless accumulation mode (JAM) negative capacitance (NC)-FinFET with reduced self-heating is proposed for the low-power Internet-of-Things (IoT) applications at 7-nm technology node.
Proceedings ArticleDOI
7-nm Nanowire FET process variation modeling using industry standard BSIM-CMG model
Ramendra Singh,Kritika Aditya,Anil K. Bansal,Parvez A. Chanawala,Terence B. Hook,Abhisek Dixit +5 more
TL;DR: In this paper, the authors have performed DC model parameter extraction and statistical process variations for 7nm target device using industry standard BSIM-CMG model using 1000 Monte Carlo simulation runs.
Journal ArticleDOI
Transient Response of 0.18- ${\mu}$ m SOI MOSFETs and SRAM Bit-Cells to Heavy-Ion Irradiation for Variable SOI Film Thickness
TL;DR: In this paper, the effect of silicon-on-insulator (SOI) thickness scaling in fully and partially depleted SOI and PD-SOI devices is analyzed for their transient response to heavy-ion irradiation.