Krzysztof Kuchcinski

Bio: Krzysztof Kuchcinski is an academic researcher from Lund University. The author has contributed to research in topics: Constraint programming & Scheduling (computing). The author has an hindex of 23, co-authored 113 publications receiving 2083 citations. Previous affiliations of Krzysztof Kuchcinski include Linköping University.

System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search

Abstract: This paper presents two heuristics for automatic hardware/software partitioning of system level specifications. Partitioning is performed at the granularity of blocks, loops, subprograms, and processes with the objective of performance optimization with a limited hardware and software cost. We define the metric values for partitioning and develop a cost function that guides partitioning towards the desired objective. We consider minimization of communication cost and improvement of the overall parallelism as essential criteria during partitioning. Two heuristics for hardware/software partitioning, formulated as a graph partitioning problem, are presented: one based on simulated annealing and the other on tabu search. Results of extensive experiments, including real-life examples, show the clear superiority of the tabu search based algorithm.

LEneS: task scheduling for low-energy systems using variable supply voltage processors

Abstract: The work presented in this paper addresses minimization of the energy consumption of a system during system-level design. The paper focuses on scheduling techniques for architectures containing variable supply voltage processors, running dependent tasks. We introduce our new approach for low-energy scheduling (LEneS) and compare it to two other scheduling methods. LEneS is based on a list-scheduling heuristic with dynamic recalculation of priorities, and assumes a given allocation and assignment of tasks to processors. Our approach minimizes the energy by choosing the best combination of supply voltages for each task running on its processor. The set of experiments we present shows that, using the LEneS approach, we can achieve up to 28% energy savings for the tightest deadlines, and up to 77% energy savings when these deadlines are relaxed by 50%.

Constraints-driven scheduling and resource assignment

Abstract: This paper describes a new method for modeling and solving different scheduling and resource assignment problems that are common in high-level synthesis (HLS) and system-level synthesis. It addresses assignment of resources for operations and tasks as well as their static, off-line scheduling. Different heterogeneous constraints are considered for these problems. These constraints can be grouped into two classes: problem-specific constraints and design-oriented constraints. They are uniformly modeled, in our approach, by finite domain (FD) constraints and solved using related constrained programming (CP) techniques. This provides a way to improve quality of final solutions. We have developed in Java a constraint solver engine, JaCoP (Java Constraint Programming), to evaluate this approach. This solver and a related framework make it possible to model different resource assignment and scheduling problems, and handle them uniformly. The JaCoP prototype system has been extensively evaluated on a number of HLS and system-level synthesis benchmarks. We have been able to obtain optimal results together with related proofs of optimality for all HLS scheduling benchmarks and for all explored design styles (except one functional pipeline design). Many system-level benchmarks can also be solved optimally. For large randomly generated task graphs, we have used heuristic search methods and obtained results that are 1--3p worse than lower bounds or optimal results. These experiments have proved the feasibility of the presented approach.

Scheduling of conditional process graphs for the synthesis of embedded systems

Abstract: We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared buses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

Automated transformation of algorithms into register-transfer level implementations

Abstract: This paper describes a high-level synthesis system, called CAMAD, for transforming algorithms into hardware implementation structures at register-transfer level. The algorithms are used to specify the behaviors of the hardware to be designed. They are first translated into a formal representation model which is based on timed Petri nets and consists of separate but related descriptions of control and data path. The formal model is used as an intermediate design representation and supports an iterative transformation approach to high-level synthesis. The basic idea is that once the behavioral specification is translated into the initial design representation, it can be viewed as a primitive implementation. Correctness-preserving transformations are then used to successively transform the initial design into an efficient implementation. Selection of transformations is guided by an optimization strategy which makes design decisions concerning operation scheduling, data path allocation, and control allocation simultaneously. The integration of these several synthesis subtasks has resulted in a better chance to reach the globally optimal solution. Experimental results show that our approach produces improved register-transfer designs, especially in the cases when the designed hardware consists of data paths and control logics that are tightly coupled. >

Teaching for quality learning at university

Abstract: by J. Biggs and C. Tang, Maidenhead, England, Open University Press, 2007, 360 pp., £29.99, ISBN-13: 978-0-335-22126-4

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Abstract: The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field. · Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes · Views of FPGA programming beyond Verilog/VHDL · Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

Multiprocessor System-on-Chip (MPSoC) Technology

Abstract: The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware subsystems to implement a system. A wide range of MPSoC architectures have been developed over the past decade. This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture. We consider some of the technological trends that have driven the design of MPSoCs. We also survey computer-aided design problems relevant to the design of MPSoCs.

Correct Hardware Design and Verification Methods

Abstract: ion and Compositional Techniques From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 E.Allen Emerson, Richard J. Trefler Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Dirk W. Hoffmann, Thomas Kropf Abstract BDDs: A Technique for Using Abstraction in Model Checking . . . 172 Edmund Clarke, Somesh Jha, Yuan Lu, Dong WangBDDs: A Technique for Using Abstraction in Model Checking . . . 172 Edmund Clarke, Somesh Jha, Yuan Lu, Dong Wang Theorem Proving Related Approaches Formal Synthesis at the Algorithmic Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Christian Blumenröhr, Viktor Sabelfeld Xs Are for Trajectory Evaluation, Booleans Are for Theorem Proving . . . . . 202 Mark Aagaard, Thomas Melham, John O’Leary Verification of Infinite State Systems by Compositional Model Checking . . 219 K.L.McMillan Symbolic Simulation/Symbolic Traversal Formal Verification of Designs with Complex Control by Symbolic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Gerd Ritter, Hans Eveking, Holger Hinrichsen Hints to Accelerate Symbolic Traversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Kavita Ravi, Fabio Somenzi Specification Languages and Methodologies Modeling and Checking Networks of Communicating Real-Time Processes . 265 Jürgen Ruf, Thomas Kropf ”Have I Written Enough Properties?” A Method of Comparison between Specification and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Sagi Katz, Orna Grumberg, Danny Geist Program Slicing of Hardware Description Languages . . . . . . . . . . . . . . . . . . . . 298 E.Clarke, M.Fujita, S.P.Rajan, T.Reps, S.Shankar, T.Teitelbaum Table of

Giotto: a time-triggered language for embedded programming

Abstract: Giotto provides an abstract programmer's model for the implementation of embedded control systems with hard real-time constraints. A typical control application consists of periodic software tasks together with a mode-switching logic for enabling and disabling tasks. Giotto specifies time-triggered sensor readings, task invocations, actuator updates, and mode switches independent of any implementation platform. Giotto can be annotated with platform constraints such as task-to-host mappings, and task and communication schedules. The annotations are directives for the Giotto compiler, but they do not alter the functionality and timing of a Giotto program. By separating the platform-independent from the platform-dependent concerns, Giotto enables a great deal of flexibility in choosing control platforms as well as a great deal of automation in the validation and synthesis of control software. The time-triggered nature of Giotto achieves timing predictability, which makes Giotto particularly suitable for safety-critical applications.