Kuntal Joardar

Bio: Kuntal Joardar is an academic researcher from Motorola. The author has contributed to research in topics: Transistor & Field-effect transistor. The author has an hindex of 9, co-authored 18 publications receiving 388 citations.

An improved MOSFET model for circuit simulation

Abstract: Problems that have continued to remain in some of the recently published MOSFET compact models are demonstrated in this paper. Of particular interest are discontinuities observed in these models at the boundary between forward and reverse mode operation. A new MOSFET model is presented that overcomes the errors present in state-of-the-art models. Comparison with measured data is also presented to validate the new model.

Circuit die having improved substrate noise isolation

Abstract: A circuit die 100 with improved substrate noise isolation may be achieved by providing a first circuit element 102 and a second circuit element 103 on a substrate 101. The first circuit element 102 generally injects noise into the substrate 101 while the second circuit element 103 is adversely affected by noise being carried in the substrate 101. To reduce the noise interference, a noise isolation ring 104-017 may be placed around the first circuit element 102 and/or the second circuit element 103 wherein the noise isolation ring is of a conducted material. A first lead 202 is electrically connected to a first circuit element 102, a second lead 205 is electrically connected to the second circuit element 103, and a third lead 201 is electrically connected to the noise isolation ring 105, wherein the third lead 201 is electrically isolated from both the first and second leads 202 and 205.

An improved analytical model for collector currents in lateral bipolar transistors

Abstract: Detailed analyses of the lateral bipolar transistor have been performed and a physically based model for the collector current developed. Hybrid mode operation of the lateral BJT in the presence of a gate electrode has been considered. Two-dimensional current flow in the base has also been taken into account without the use of empirical parameters. Comparisons with numerical simulations, existing models, and experimental data have been performed to demonstrate the accuracy and improvements realized by the new model. >

Substrate crosstalk in BiCMOS mixed mode integrated circuits

Abstract: A comparison of several crosstalk reduction schemes using two-dimensional device simulation and measurements on silicon has shown that while SOI based processes provide high isolation from crosstalk, fully junction isolated wells can provide equal or better crosstalk immunity at a lesser expense. Simple guard ring substrate contacts appear to be the technique best suited for preventing cross-talk at high operating frequencies. A lumped parameter equivalent circuit has also been developed to simulate fully junction isolated wells in SPICE.

A Physically-Based Compact Model for LDMOS Transistors

Abstract: This paper presents a physically based model for LDMOS transistors. The model advances the state-of-the-art by using a formulation applicable across a wide voltage range, by accounting for the distributed parasitic metal effects, and by properly modeling the bias dependence of parasitic capacitances. The model is implemented in Motorola’s internal simulator MCSPICE.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation

Abstract: This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context

Intergrated circuit with coaxial isolation and method

Abstract: A die 810 has an outer, annular via 814 filled with conductive material in order to electrically shield an inner via 816. A die 820 can be electrically shielded from another area 822 by use of a wall 823 having a trench with oxidized side walls and a conductive filling.

Fully-depleted SOI CMOS for analog applications

Abstract: Fully-depleted (FD) SOI MOSFETs offer near-ideal properties for analog applications. In particular their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and the reduced body effect permits one to fabricate more efficient pass gates. The excellent behavior of SOI MOSFETs at high temperature or at gigahertz frequencies is outlined as well.

Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model

Abstract: In this paper, the implications of inversion charge linearization in compact MOS transistor modeling are discussed. The charge-sheet model provides the basic relation among inversion charge and applied potentials, via the implicit surface potential. A rigorous derivation of simpler relations among inversion charge and applied external potentials is provided, using the technique of inversion charge linearization versus surface potential. The new concept of the pinch-off surface potential and a new definition of the inversion charge linearization factor are introduced. In particular, we show that the EKV charge-based model can be considered as an approximation to the more general approach presented here. An improvement to the EKV charge-based model is proposed in the form of a more accurate charge–voltage relationship. This model is analyzed in detail and shows an excellent agreement with the charge sheet model. The normalization of voltages, current and charges, as motivated by the inversion charge linearization, results in a major simplification in compact modeling in static as well as non-quasi-static derivations.