Kuo-Huang Chang

Bio: Kuo-Huang Chang is an academic researcher from National Taiwan Normal University. The author has contributed to research in topics: Encryption & Cipher. The author has an hindex of 4, co-authored 4 publications receiving 73 citations.

High throughput 32-bit AES implementation in FPGA

Abstract: Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature.

Embedded a low area 32-bit AES for image encryption/decryption application

Abstract: Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). However, lower throughput and low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.

The five modes AES applications in sounds and images

Abstract: This paper presents the applications of Advanced Encryption Standard (AES) in audio and video signals. Like the ciphertext is completely different from the plaintext in AES operation, so the encrypted audio or visual signal should have the same effect. The experiments reveal the encrypted signals are so much different from the original ones that they become random noises. However, in some cases, a kind of pattern may appear within the encrypted noise in the ECB mode operation, causing a kind of sounds being heard during the play back of encrypted audio noise, or some patterns appeared amid the cipher images, due to having the same audio or video inputs which can be mostly reduced by compressing before encryption. This paper presents the ways, featured in the other four modes of AES, to make the same inputs different without compressing. The high speed parallel operations for the five modes are also discussed.

The AES application in image using different operation modes

Abstract: This paper presents an application of AES (Advanced Encryption Standard) operations in image encryption and decryption. The encrypted cipher images always display the uniformly distributed RGB pixels. It looks like the noise of TV without signals. However, in some cases the ECB mode operation may appear a kind of pattern in the area related to the portion of the original image having the same color. The reason for the pattern generation and the four operation modes of CBC, CFB, OFB and CTR which have the features to eliminate the patterns are discussed, in terms of the degree of random noise in cipher image as well as the feasibility of parallel operation in cipher blocks for high speed processing.

DeepEDN: A Deep-Learning-Based Image Encryption and Decryption Network for Internet of Medical Things

Abstract: Internet of Medical Things (IoMT) can connect many medical imaging equipment to the medical information network to facilitate the process of diagnosing and treating doctors. As medical image contains sensitive information, it is of importance yet very challenging to safeguard the privacy or security of the patient. In this work, a deep-learning-based image encryption and decryption network (DeepEDN) is proposed to fulfill the process of encrypting and decrypting the medical image. Specifically, in DeepEDN, the cycle-generative adversarial network (Cycle-GAN) is employed as the main learning network to transfer the medical image from its original domain into the target domain. The target domain is regarded as “hidden factors” to guide the learning model for realizing the encryption. The encrypted image is restored to the original (plaintext) image through a reconstruction network to achieve image decryption. In order to facilitate the data mining directly from the privacy-protected environment, a region of interest (ROI)-mining network is proposed to extract the interesting object from the encrypted image. The proposed DeepEDN is evaluated on the chest X-ray data set. Extensive experimental results and security analysis show that the proposed method can achieve a high level of security with a good performance in efficiency.

Parallel AES Encryption Engines for Many-Core Processor Arrays

Abstract: By exploring different granularities of data-level and task-level parallelism, we map 16 implementations of an Advanced Encryption Standard (AES) cipher with both online and offline key expansion on a fine-grained many-core system. The smallest design utilizes only six cores for offline key expansion and eight cores for online key expansion, while the largest requires 107 and 137 cores, respectively. In comparison with published AES cipher implementations on general purpose processors, our design has 3.5-15.6 times higher throughput per unit of chip area and 8.2-18.1 times higher energy efficiency. Moreover, the design shows 2.0 times higher throughput than the TI DSP C6201, and 3.3 times higher throughput per unit of chip area and 2.9 times higher energy efficiency than the GeForce 8800 GTX.

An Enhanced WLAN Security System With FPGA Implementation for Multimedia Applications

Abstract: Maintaining a high level of data security with a low impact on system performance is more challenging in wireless multimedia applications. Protocols that are used for wireless local area network (WLAN) security are known to significantly degrade performance. In this paper, we propose an enhanced security system for a WLAN. Our new design aims to decrease the processing delay and increase both the speed and throughput of the system, thereby making it more efficient for multimedia applications. Our design is based on the idea of offloading computationally intensive encryption and authentication services to the end systems' CPUs. The security operations are performed by the hosts' central processor (which is usually a powerful processor) before delivering the data to a wireless card (which usually has a low-performance processor). By adopting this design, we show that both the delay and the jitter are significantly reduced. At the access point, we improve the performance of network processing hardware for real-time cryptographic processing by using a specialized processor implemented with field-programmable gate array technology. Furthermore, we use enhanced techniques to implement the Counter (CTR) Mode with Cipher Block Chaining Message Authentication Code Protocol (CCMP) and the CTR protocol. Our experiments show that it requires timing in the range of 20–40 $\mu\mbox{s}$ to perform data encryption and authentication on different end-host CPUs (e.g., Intel Core i5, i7, and AMD 6-Core) as compared with 10–50 ms when performed using the wireless card. Furthermore, when compared with the standard WiFi protected access II (WPA2), results show that our proposed security system improved the speed to up to 3.7 times.