With the advancement of VLSI technology, the effect of jitter is becoming more critical on high speed signals. To negate the effect of jitter on these signals, the causes of jitter in a circuit need to be identified by decomposing the jitter. In this paper, a comparative analysis of various jitter estimation techniques is presented. The statistical domain methods are based on fitting techniques while the frequency domain methods are based on frequency spectrum analysis. This work describes both statistical domain methods and frequency domain methods. Further, their strengths and limitations are discussed. The algorithms are implemented in MATLAB and the results are extensively verified with Agilent ADS.

A comparative analysis of jitter estimation techniques

Pattern jitter is a primary contributor to the increase of the bit error rate (BER) in high-speed communications, which occurs in large part due to duty cycle distortion (DCD). By considering DCD caused by transmission links and the distribution of jitter in DCD due to the pattern of the transmission link, this paper proposes a precise control method based on the cross point of the eye diagram to minimize the jitter associated with DCD and to effectively decrease the BER of high-speed digital communications. By capitalizing on the theoretical basis that the main form of DCD is the offset of the cross point of the eye diagram, the technology presented here reconstructs the pattern waveform by using a digital method and incorporates a time variable to precisely control the data edge position during the reconstruction process, thereby stabilizing the cross point at 50% to correct its drift. Accordingly, after fanning out the original pattern buffer and then passing two controllable delay lines with different delays through the buffer in a process that is driven by digital logic operation, the cross point of the waveform is reconstructed by changing the relative time delay of the two signals. As a result, the change in the position of the cross point of the eye diagram is transformed into the precise control of the relative time delay, minimizing the DCD jitter. The theoretical model is verified by experiments, indicating that this method can control the cross point of the non-return-to-zero (NRZ) pattern in the range of 30% to 70% under 3 Gbps with a resolution as great as 1%. Furthermore, this approach can solve the problem of cross point drift of the eye diagram and can significantly decrease the BER caused by DCD jitter.

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Minimizing the Jitter of Duty Cycle Distortion Correction Technology Based on Cross Point Eye Diagram Correction

Today's communication systems have achieved data rates
in the range of multi-gigabits per second (Gb/s). With such an
incessant escalation in data rates, design engineers are working
hard to maintain the performance of these high-speed systems. At
higher data rates, it is imperative to preserve the system
performance by estimating the impairments of signal. These
impairments are mainly due to the frequency dependent nature of
transmitters, channels, and receivers in a communication system.
Jitter plays a major role in contributing to these impairments
thereby, degrading the performance of communication systems. As the
speed of data transfer increases, the effects of jitter become more
critical with tighter jitter budgets. In order to reduce the
effects of jitter in a system, it is crucial to understand its
causes and characteristics. In this thesis, the fundamentals of
jitter along with its components and sources are reviewed. It
illustrates several parameters relevant to the analysis of jitter
and its types. This is followed by an overview of some traditional
techniques used for jitter measurement and modeling such as the
sampling oscilloscopes, bit error ratio tester (BERT), time
interval analyzer (TIA), and some state-of-the-art algorithms such
as the Tail fit, Peak distortion analysis (PDA), and direct
computation of probabilities algorithms. These techniques are
well-elucidated with examples as well as their pros and cons. This
thesis presents an implementation of the most recent link
statistical signaling technique for modeling jitter, in the
presence of CMOS non-linearity observed in receivers. This
algorithm is based on a superposition technique using HashMaps for
determining the accurate logic level of digital data bits, in the
presence of jitter. This approach deals with the overall effect of
unwanted alterations observed on a data bit positioned at the
cursor, contributed by neighboring bits in a digital data stream.
In this technique, HashMaps are employed to sustain the
computational intricacies involved in this algorithm. The time
required for the execution is also reduced, making it an efficient
technique for this implementation. The execution time of this
technique is reduced by more than a third as compared to a prior
implementation of the Link Analysis algorithm called ‘Bin
Multiplication’. This technique is implemented for non-return to
zero (NRZ), which is the most preferred signaling scheme in
high-speed digital systems. Most of the jitter modeling techniques
are based on the assumption of linear behavior of components in
communication systems. However, in reality, receivers exhibit
non-linear traits and this aspect substantially detriments the
performance of a system. Thus, the statistical analysis for jitter
measurement in terms of bit error rate (BER), is extended to
account for the receiver’s non-linearity. In this research, the
voltage characteristic of complementary metal-oxide semiconductor
(CMOS) receivers is nominated for modeling the non-linearity in
terms of hyperbolic tangent. The…

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An Efficient Implementation Of Link Analysis Algorithm In High-Speed Interfaces for NRZ In The Presence Of CMOS Non-Linearity In Receivers

Jitter can be generally modeled as a superposition of an unbounded random component that follows a Gaussian distribution and a bounded deterministic component. It is usually assumed that the probability distribution of total jitter for very large values of jitter tends to a purely Gaussian distribution. The standard deviation of this Gaussian distribution is identical to the standard deviation of the random component and the mean value of the distribution is related to the deterministic component. A mathematical justification for this assumption is, however, lacking in the literature. In this work, a general asymptotic expression is derived for the tail of the total jitter distribution. It is shown that, to first order, the tail of the distribution can be expressed as a Gaussian function divided by a power function of jitter. Asymptotic expressions for the cumulative distribution function and the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> -scale are also derived. The implications of these results for the accuracy of broadly accepted tail fitting routines are discussed. 

The Accuracy of the Gaussian Tail and Dual Dirac Model in Jitter Histogram and Probability Density Functions

Jitter can be generally modeled as a superposition of an unbounded random component that follows a Gaussian distribution and a bounded deterministic component. It is usually assumed that the probability distribution of total jitter for very large values of jitter tends to a purely Gaussian distribution. The standard deviation of this Gaussian distribution is identical to the standard deviation of the random component and the mean value of the distribution is related to the deterministic component. A mathematical justification for this assumption is, however, lacking in the literature. In this work, a general asymptotic expression is derived for the tail of the total jitter distribution. It is shown that, to first order, the tail of the distribution can be expressed as a Gaussian function divided by a power function of jitter. Asymptotic expressions for the cumulative distribution function and the Q-scale are also derived. The implications of these results for the accuracy of broadly accepted tail fitting routines are discussed.

Random jitter (RJ) estimation based on Tail Fit algorithm are generally inaccurate in presence of deterministic components like the presence of sinusoidal jitter (SJ) and duty cycle distortion (DCD). Addition of deterministic jitter changes the standard deviation of the tail region of resulting jitter probability density function. A new methodology for random jitter estimation in presence of sinusoidal jitter and duty cycle distortion is presented. The method involves calculation of mathematical correction factor, which are derived and used to calculate the precise value of random jitter. The proposed methodology is validated by inducing known jitter sources in real channel simulator of ADS from Agilent.

Mitigating the impact of sinusoidal jitter and duty cycle distortion on random jitter estimation by Tailfit algorithm

Level shifters form an indispensable part of modern system on chips (SoCs) with their use encompassing multi-VDD logic designs [1], voltage stacking designs[2] and high voltage designs[3]. Traditionally, level shifters have been characterized using energy-delay curves (or correspondingly the energy-delay product) [2]. All the aforementioned applications provide the level shifter’s higher supply voltage through an external pin. Also, the primary objective in the previously mentioned applications has been reduction in energy consumption. Thus, energy-delay product is an appropriate figure-of merit (FOM) for these applications. However, unlike these applications certain analog/mixed signal(AMS) applications like that in [4] employ charge-pumps to generate the higher supply voltages. The FOM of energy-delay product is no longer appropriate in these cases for two reasons. First, the use of energy delay curves to characterize and choose the appropriate level shifter architecture ignores the energy consumed by the charge pumps to generate the higher voltages and can eventually lead to an overall larger energy consumption. Secondly, since the current from the higher voltage is provided through a charge reservoir (capacitor in most cases), voltage droop during switching should also be accounted by the FOM. Optimizing the energy-delay product does not account for this effect. We therefore argue that charge-delay product (or correspondingly the charge-delay curves) is a better FOM to compare level shifters to be used in such applications. The “charge” of concern here refers to the charge consumed through the higher supply voltage. One might argue that charge-delay optimization is equivalent to energy-delay optimization. However, we would like to emphasize the fact that our objective is to obtain the optimization between the charge consumed from the higher supply voltage and the delay of the level shifter. This FOM allows for trading off higher energy consumption from the lower supply voltage for a lower charge consumption from the higher supply voltage.

Level Shifters for Charge Constrained Applications

On-chip testing for analog/mixed signal circuits helps improve reliability of safety-critical systems by enabling infield testing. It also alleviates the problems of increasing test costs. A low-cost high accuracy stimulus generator for on-chip spectral testing is proposed. The generator uses a low-cost DAC which requires minimal design and re-engineering efforts, in conjunction with INL based digital pre-distortion to calibrate its linearity performance. DAC output measurement, DAC INL estimation and DAC linearity calibration are all performed on-chip. Measurement results in 40nm bulk CMOS technology demonstrate that the circuit is capable of producing a rail-to-rail differential signal with THD of -75 dB and SFDR of 79dB. The proposed solution is a major step forward in demonstrating the feasibility of synthesizable built-in-test solutions for high-accuracy embedded analog and mixed signal functions.

Kushagra Bhatheja

Papers

Mitigating the impact of sinusoidal jitter and duty cycle distortion on random jitter estimation by Tailfit algorithm

Level Shifters for Charge Constrained Applications

Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing