We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Memory effects are ubiquitous in nature and are particularly relevant at the nanoscale where the dynamical properties of electrons and ions strongly depend on the history of the system, at least within certain time scales. We review here the memory properties of various materials and systems which appear most strikingly in their non-trivial, time-dependent resistive, capacitative and inductive characteristics. We describe these characteristics within the framework of memristors, memcapacitors and meminductors, namely memory-circuit elements with properties that depend on the history and state of the system. We examine basic issues related to such systems and critically report on both theoretical and experimental progress in understanding their functionalities. We also discuss possible applications of memory effects in various areas of science and technology ranging from digital to analog electronics, biologically inspired circuits and learning. We finally discuss future research opportunities in the field.

Memory effects in complex materials and nanoscale systems

Power consumption is a major factor that limits the performance of computers. We survey the “state of the art” in techniques that reduce the total power consumed by a microprocessor system over time. These techniques are applied at various levels ranging from circuits to architectures, architectures to system software, and system software to applications. They also include holistic approaches that will become more important over the next decade. We conclude that power management is a multifaceted discipline that is continually expanding with new techniques being developed at every level. These techniques may eventually allow computers to break through the “power wall” and achieve unprecedented levels of performance, versatility, and reliability. Yet it remains too early to tell which techniques will ultimately solve the power problem.

/pdf/power-reduction-techniques-for-microprocessor-systems-3dfczj5khm.pdf

Power reduction techniques for microprocessor systems

Technology roadmaps help predict requirements for future technologies and guide ongoing technology research and development. The International Technology Roadmap for Semiconductors (ITRS) [1] has been published since 1999; it is fully revised in odd-numbered years and updated in even-numbered years. In this paper, we describe a modeling framework to predict future characteristics and implied technology requirements of the ITRS microprocessor (MPU) ‘system driver’, following Moore's Law scaling under power constraints. The outcomes of this modeling effort are the basis of ITRS updates to be published in the 2009 ITRS edition.

/pdf/a-power-constrained-mpu-roadmap-for-the-international-2nst94cket.pdf

A power-constrained MPU roadmap for the International Technology Roadmap for Semiconductors (ITRS)

As optical lithography advances into the 45nm technology node and beyond, new manufacturing-aware design requirements have emerged. We address layout design for interference-assisted lithography (IAL), a double exposure method that combines maskless interference lithography (IL) and projection lithography (PL); cf. hybrid optical maskless lithography (HOMA) in [2] and [3]. Since IL can generate dense but regular pitch patterns, a key challenge to deployment of IAL is the conversion of existing designs to regular-linewidth, regular-pitch layouts. In this paper, we propose new 1-D regular pitch SRAM bitcell layouts which are amenable to IAL. We evaluate the feasibility of our bitcell designs via lithography simulations and circuit simulations, and confirm that the proposed bitcells can be successfully printed by IAL and that their electrical characteristics are comparable to those of existing bitcells.

/pdf/32nm-1-d-regular-pitch-sram-bitcell-design-for-interference-304r6xbgu3.pdf

32nm 1-D Regular Pitch SRAM Bitcell Design for Interference-Assisted Lithography

The multi-threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low V/sub th/ transistors are used to implement the desired function, the high V/sub th/ transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for Samsung's 0.18 /spl mu/m process, (ii) propose a new special flip-flop which keeps valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a personal digital assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18 /spl mu/m process. The fabricated PDA processor operates at 333 MHz, and consumes about 2 /spl mu/W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.

/pdf/an-mtcmos-design-methodology-and-its-application-to-mobile-54eh7m8j9m.pdf

An MTCMOS design methodology and its application to mobile computing

As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power, performance, and area has become crucially important. In this work, we develop accurate architecture-level on-chip router cost models using machine-learning-based regression techniques. Compared against existing models (e.g., ORION 2.0 and parametric models), our models reduce estimation error by up to 89% on average.

Accurate Machine-Learning-Based On-Chip Router Modeling

The value of guardband reduction is a critical open issue for the semiconductor industry. For example, due to competitive pressure, foundries have started to incent the design of manufacturing-friendly ICs through reduced model guardbands when designers adopt layout restrictions. The industry also continuously weighs the economic viability of relaxing process variation limits in the technology roadmap (available: http://public.itrs.net). Our work gives the first-ever quantification of the impact of model guardband reduction on outcomes from the synthesis, place and route (SPR 40% is the amount of guardband reduction reported by IBM for a variation-aware timing methodology. For the embedded processor core we observe up to 8% standard-cell area reduction, 7% routed wirelength reduction, 5% dynamic power reduction, and 10% leakage power reduction at 30% guardband reduction. We also report a set of fine-grain SPICE simulations that accurately assesses the impact of process guardband reduction, as distinguished from overall guardband reductions, on yield. We observe up to 4% increase in number of good dies per wafer at 27% process guardband reduction (i.e., with fixed voltage and temperature). Our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing-friendly design practices.

/pdf/impact-of-guardband-reduction-on-design-outcomes-a-bhww2v4tsk.pdf

Kwangok Jeong

Papers

A power-constrained MPU roadmap for the International Technology Roadmap for Semiconductors (ITRS)

32nm 1-D Regular Pitch SRAM Bitcell Design for Interference-Assisted Lithography

An MTCMOS design methodology and its application to mobile computing

Accurate Machine-Learning-Based On-Chip Router Modeling

Impact of Guardband Reduction On Design Outcomes: A Quantitative Approach