Kyosun Kim

Bio: Kyosun Kim is an academic researcher from Incheon National University. The author has contributed to research in topics: NOR gate & Logic synthesis. The author has an hindex of 5, co-authored 18 publications receiving 199 citations.

Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations

Abstract: This brief presents a stateful logic gate based on memristive devices that functions as high-fan-in NOR gates. The proposed logic structure executes multiple implications concurrently in a single step and thus enables fast logic operations reducing the number of pipeline steps. By mapping the logic units to the field-programmable nanowire interconnect fabric, a reconfigurable 2-D logic array for general-purpose functions can be implemented by configuring nanowire crossbar switches.

Field Programmable Stateful Logic Array

Abstract: Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. The proposed architecture mapped to the field programmable nanowire interconnect fabric produces a field programmable stateful logic array, in which general-purpose computation functions can be implemented by configuring only nonvolatile nanowire crossbar switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely, material implication, cannot fan out, a new basic AND operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. The fine-grain ultradeep constant-throughput pipeline properties pose new design automation problems. We address some of the issues, in particular logic representation using OR-inverter graphs, two-level optimization synthesis strategy, data synchronization with data forwarding, stall-free pipelined finite state machines, and constraints for synthesis and mapping onto the fabric.

Effects of gate structures on the RF performance in PD SOI MOSFETs

Abstract: The radio-frequency (RF) performance of PD silicon-on-insulator metal oxide semiconductor field effect transistors with T-gate and H-gate structures has been investigated. Our measurement shows that H-gate devices have larger cutoff frequency and smaller minimum noise figure than T-gate devices. This improved RF performance in H-gate devices can be explained mainly by the enhancement of transconductance resulting from the gate extension induced inversion charges and the low gate resistance. We conclude that the H-gate structure is superior to the T-gate structure for the design of the low-noise amplifier (LNA).

Stateful logic pipeline architecture

Abstract: Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel Since basic operation of the stateful logic, namely material implication, cannot fan out, a new AND basic operation which can duplicate output is proposed The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate Due to the fine-grain ultra-deep constant-throughput pipeline properties, design paradigm shifts are required We address some of the issues, in particular logic representation using Staged OR-NOR Graphs (SONGs), and data synchronization with data forwarding

Micropreemption synthesis: an enabling mechanism for multitask VLSI systems

Abstract: Task preemption is a critical enabling mechanism in multitask very large scale integration (VLSI) systems. On preemption, data in the register files must be preserved for the task to be resumed. This entails extra memory to preserve the context and additional clock cycles to save and restore the context. In this paper, techniques and algorithms to incorporate micropreemption constraints during multitask VLSI system synthesis are presented. Specifically, algorithms to insert and refine preemption points in scheduled task graphs subject to preemption latency constraints, techniques to minimize the context switch overhead by considering the dedicated registers required to save the state of a task on preemption and the shared registers required to save the remaining values in the tasks, and a controller-based scheme to preclude the preemption-related performance degradation by: 1) partitioning the states of a task into critical sections; 2) executing the critical sections atomically; and 3) preserving atomicity by rolling forward to the end of the critical sections on preemption have been developed. The effectiveness of all approaches, algorithms, and software implementations is demonstrated on real examples. Validation of all the results is complete in the sense that functional simulation is conducted to complete layout implementation.

MAGIC—Memristor-Aided Logic

Abstract: Memristors are passive components with a varying resistance that depends on the previous voltage applied across the device. While memristors are naturally used as memory, memristors can also be used for other applications, including logic circuits. In this brief, a memristor-only logic family, i.e., memristor-aided logic (MAGIC), is presented. In each MAGIC logic gate, memristors serve as an input with previously stored data, and an additional memristor serves as an output. The topology of a MAGIC nor gate is similar to the structure of a common memristor-based crossbar memory array. A MAGIC nor gate can therefore be placed within memory, providing opportunities for novel non-von Neumann computer architectures. Other MAGIC gates also exist (e.g., and , or , not , and nand ) and are described in this brief.

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies

Abstract: Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process. The logical state is determined by the resistance of the memristor. This logic family can be integrated within a memristor-based crossbar, commonly used for memory. In this paper, a methodology for designing this logic family is proposed. The design methodology is based on a general design flow, suitable for all deterministic memristive logic families, and includes some additional design constraints to support the IMPLY logic family. An IMPLY 8-bit full adder based on this design methodology is presented as a case study.

If it’s pinched it’s a memristor

Abstract: This chapter consists of two parts. Part I gives a circuit-theoretic foundation for the first four elementary nonlinear 2-terminal circuit elements, namely, the resistor, the capacitor, the inductor, and the memristor. Part II consists of a collection of colorful “Vignettes” with carefully articulated text and colorful illustrations of the rudiments of the memristor and its characteristic fingerprints and signatures. It is intended as a self-contained pedagogical primer for beginners who have not heard of memristors before.

If It's Pinched It's a Memristor.

Abstract: This chapter consists of two parts. Part I gives a circuit-theoretic foundation for the first four elementary nonlinear 2-terminal circuit elements, namely, the resistor, the capacitor, the inductor, and the memristor. Part II consists of a collection of colorful “Vignettes” with carefully articulated text and colorful illustrations of the rudiments of the memristor and its characteristic fingerprints and signatures. It is intended as a self-contained pedagogical primer for beginners who have not heard of memristors before.