The rapid development of information technology has led to urgent requirements for high efficiency and ultralow power consumption. In the past few decades, neuromorphic computing has drawn extensive attention due to its promising capability in processing massive data with extremely low power consumption. Here, we offer a comprehensive review on emerging artificial neuromorphic devices and their applications. In light of the inner physical processes, we classify the devices into nine major categories and discuss their respective strengths and weaknesses. We will show that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry. Meanwhile, the recently developed electrolyte-gated synaptic transistors have demonstrated outstanding energy efficiency, linearity, and symmetry, but their stability and scalability still need to be optimized. Other emerging synaptic structures, such as ferroelectric, metal–insulator transition based, photonic, and purely electronic devices also have limitations in some aspects, therefore leading to the need for further developing high-performance synaptic devices. Additional efforts are also demanded to enhance the functionality of artificial neurons while maintaining a relatively low cost in area and power, and it will be of significance to explore the intrinsic neuronal stochasticity in computing and optimize their driving capability, etc. Finally, by looking into the correlations between the operation mechanisms, material systems, device structures, and performance, we provide clues to future material selections, device designs, and integrations for artificial synapses and neurons.

A comprehensive review on emerging artificial neuromorphic devices

Artificial Intelligence in Healthcare: Review and Prediction Case Studies

Wearable devices are a fast-growing technology with impact on personal healthcare for both society and economy. Due to the widespread of sensors in pervasive and distributed networks, power consumption, processing speed, and system adaptation are vital in future smart wearable devices. The visioning and forecasting of how to bring computation to the edge in smart sensors have already begun, with an aspiration to provide adaptive extreme edge computing. Here, we provide a holistic view of hardware and theoretical solutions toward smart wearable devices that can provide guidance to research in this pervasive computing era. We propose various solutions for biologically plausible models for continual learning in neuromorphic computing technologies for wearable sensors. To envision this concept, we provide a systematic outline in which prospective low power and low latency scenarios of wearable sensors in neuromorphic platforms are expected. We successively describe vital potential landscapes of neuromorphic processors exploiting complementary metal-oxide semiconductors (CMOS) and emerging memory technologies (e.g., memristive devices). Furthermore, we evaluate the requirements for edge computing within wearable devices in terms of footprint, power consumption, latency, and data size. We additionally investigate the challenges beyond neuromorphic computing hardware, algorithms and devices that could impede enhancement of adaptive edge computing in smart wearable devices.

/pdf/adaptive-extreme-edge-computing-for-wearable-devices-23uhxby4po.pdf

Adaptive Extreme Edge Computing for Wearable Devices.

Wearable devices are a fast-growing technology with impact on personal healthcare for both society and economy. Due to the widespread of sensors in pervasive and distributed networks, power consumption, processing speed, and system adaptation are vital in future smart wearable devices. The visioning and forecasting of how to bring computation to the edge in smart sensors have already begun, with an aspiration to provide adaptive extreme edge computing. Here, we provide a holistic view of hardware and theoretical solutions towards smart wearable devices that can provide guidance to research in this pervasive computing era. We propose various solutions for biologically plausible models for continual learning in neuromorphic computing technologies for wearable sensors. To envision this concept, we provide a systematic outline in which prospective low power and low latency scenarios of wearable sensors in neuromorphic platforms are expected. We successively describe vital potential landscapes of neuromorphic processors exploiting complementary metal-oxide semiconductors (CMOS) and emerging memory technologies (e.g. memristive devices). Furthermore, we evaluate the requirements for edge computing within wearable devices in terms of footprint, power consumption, latency, and data size. We additionally investigate the challenges beyond neuromorphic computing hardware, algorithms and devices that could impede enhancement of adaptive edge computing in smart wearable devices.

https://www.zora.uzh.ch/id/eprint/200278/1/2012.14937.pdf

Adaptive Extreme Edge Computing for Wearable Devices

Photonic Synapses for Ultrahigh-Speed Neuromorphic Computing

In this work, we fabricated a dual gate positive feedback field-effect transistor (FBFET) integrated with CMOS. We investigated the DC and transient characteristics of the FBFET. The fabricated FBFET has an extremely low sub-threshold slope of less than 2.3 mV/dec and low off-current. We also propose an analog integrated-and-fire neuron circuit incorporating a FBFET, which significantly reduces the power dissipation of hardware neural networks. In a conventional neuron circuit using a membrane capacitor to integrate input pulses, most of the energy is consumed by the first inverter stage connected to the capacitor. Since the membrane capacitor is charged slowly compared to digital logic, a large amount of short-circuit current flows between Vdd and ground in the first inverter during this period. In the proposed neuron circuit, the short-circuit current is significantly suppressed by adopting a FBFET in the inverter. Through TCAD mixed mode simulation of the device and the circuit, we compare the energy consumption of a conventional and the proposed neuron circuits. In a single neuron circuit with microsecond duration pulses, 58% of the energy consumption is reduced by incorporating a FBFET. We performed SPICE compact modeling of FBFET, and its parameters were fitted to match the measurement results of the fabricated FBFET. Then, we conducted a circuit simulation to verify the operating neural networks. We implemented a single layer spiking neural network (SNN) that had resistive synaptic devices. In the SNN simulation, approximately 94% of the average power consumption of all output neurons was reduced.

Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation

This letter presents a novel method for the sensitivity analysis between a process parameter and an electrical characteristic using the gradient of a neural network (NN). As devices become scaled and new emerging devices appear, it becomes more complex and the development of a SPICE model takes considerable time. Sensitivity analysis based on NN can accurately obtain the sensitivity even if the data are correlated with each other and have a non-linear relationship. The proposed method can be used to model the device characteristics and optimize process control through component analysis. It is verified using a feedback field-effect transistor (FBFET), one of the emerging neuromorphic devices. We execute experiments with 1055 TCAD simulations calibrated based on 33 measurement data for various process parameters and bias combinations and compare the results with a general linear model (GLM). In this work, we select 7 input parameters and extract voltage threshold ( ${V} _{\text {th}}$ ) and on-current ( ${I} _{\text {ON}}$ ), which are key characteristics of FBFET, as output parameters, and analyze the sensitivity with our method and provide a process control solution. This letter shows an important role in filling the gap between the emerging device proposal and the development of the SPICE model.

Sensitivity Analysis Based on Neural Network for Optimizing Device Characteristics

We have developed a capacitor-less I&F neuron circuit with a dual gate positive feedback fieldeffect transistor (FBFET) and successfully co-integrated FBFET and CMOS in a wafer. By implementing the neuron circuit with FBFET, we can overcome the limits of conventional CMOS, reduce energy consumption, and imitate the biological neuron. The floating body of the FBFET can replace the membrane capacitor that occupies a large area and performs leaky integration of the neuron. Due to the extremely low sub-threshold swing of the FBFET (less than 0.528mv/dc), energy consumption of the neuron is significantly reduced by suppressing sub-threshold current. Finally, we analyzed the fabricated neuron circuit operation, retention time of the integrated charges and energy consumption compare to conventional CMOS neuron circuit.

/pdf/a-low-energy-high-density-capacitor-less-i-f-neuron-circuit-1pf576ul9m.pdf

A Low-Energy High-Density Capacitor-Less I&F Neuron Circuit Using Feedback FET Co-Integrated With CMOS

A partially depleted silicon-on-insulator MOSFET is analyzed over a wide temperature range from 380K to 80K to characterize memory performance at cryogenic temperatures and verify its feasibility as a cryogenic memory cell. In the Shockley-Read-Hall theory, the generation–recombination rate decreases with decreasing temperature, therefore, the retention properties of the capacitorless single transistor DRAM cell are greatly improved as temperature decreases. The static and dynamic retention times increase sharply as temperature decreases. The dynamic retention time reaches up to ~3.5 s at 80K, which is ~104 times larger than that at 300K. In addition, as the temperature decreases, the current sensing margin also increases more than 2.5 times at 80K ( $\sim 11~\mu \text{A}$ ) compared to that at 300K, due to the improved dynamic retention characteristics and the increased transconductance.

Kyungchul Park

Papers

Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation

Sensitivity Analysis Based on Neural Network for Optimizing Device Characteristics

A Low-Energy High-Density Capacitor-Less I&F Neuron Circuit Using Feedback FET Co-Integrated With CMOS

Characterization of a Capacitorless DRAM Cell for Cryogenic Memory Applications

A Novel Vector-matrix Multiplication (VMM) Architecture based on NAND Memory Array