Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

An L-shaped tunnel FET (TFET), which features band-to-band tunneling (BTBT) perpendicular to the channel direction, is experimentally demonstrated for the first time. It is more scalable than other vertical-BTBT-based TFET designs and provides more than $1000\times $ higher ON-current ( $I_{{\mathrm{\scriptscriptstyle ON}}}$ ) than a conventional planar TFET with the same gate overdrive ( $V_{\mathrm{ov}}$ ) of 0.8 V, due to improved subthreshold swing ( $S$ ) and larger tunnel junction area. Its temperature dependence, constant $S$ , and nonlinear output characteristics are discussed.

Demonstration of L-Shaped Tunnel Field-Effect Transistors

Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

Nanowire Electronics: From Nanoscale to Macroscale

Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher on-currents of n- and p-TFETs of > 10 μA/μm at VDS=0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <; 60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very lowVDD=0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD=1.0 V.

Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

We present novel multifunctional nanocircuits built from nanowire transistors that uniquely feature equal electron and hole conduction. Thereby, the mandatory requirement to yield energy efficient circuits with a single type of transistor is shown for the first time. Contrary to any transistor reported up to date, regardless of the technology and semiconductor materials employed, the dually active silicon nanowire channels shown here exhibit an ideal symmetry of current–voltage device characteristics for electron (n-type) and hole (p-type) conduction as evaluated in terms of comparable currents, turn-on threshold voltages, and switching slopes. The key enabler to symmetry is the selective tunability of the tunneling transmission of charge carriers as rendered by the combination of the nanometer-scale dimensions of the junctions and the application of radially compressive strain. To prove the advantage of this concept we integrated dually active transistors into cascadable and multifunctional one-dimension...

Dually active silicon nanowire transistors and circuits with equal electron and hole transport.

In this letter, we report that the source and channel Fermi-Dirac distributions in interband-tunneling-controlled transistors play a fundamental role on the modulation of the injected current. We explain the superlinear onset of the output characteristics based on the occupancy function modulation. Thus, we point out that, along with the tunneling barrier transparency, the availability of carriers and empty states, at the beginning and at the end of the tunneling path, respectively, should be always taken into account for a proper modeling of tunnel FETs.

Understanding the Superlinear Onset of Tunnel-FET Output Characteristic

This paper reports on the top-down fabrication and electrical performance of silicon nanowire (SiNW) gate-all-around (GAA) n-type and p-type MOSFET devices integrated on bulk silicon using a local-silicon-on-insulator (SOI) process The proposed local-SOI fabrication provides various nanowire cross sections: Omega-like, pentagonal, triangular, and circular, all controlled by isotropic etching using nitride spacers and silicon sacrificial oxidation The reported top-down SiNW fabrication offers excellent control of wire doping and placement, as well as ohmic source and drain contacts A particular feature of the process is the buildup of a tensile strain in all suspended nanowires, attaining values of few percents, reflected in stress values higher than 2-3 GPa A very high yield (>90%) is obtained in terms of functionality of long-channel SiNW GAA mosfet Device characteristics are reported from cryogenic temperature (T = 5 K) up to 150 degC, and promising characteristics in terms of low-field electron mobility, threshold voltage control, and subthreshold slope are demonstrated Low field mobility for electrons up to 850 cm2 /Vmiddots is reported at room temperature in suspended devices with triangular cross sections; this mobility enhancement is explained by the process-induced tensile strain In short, suspended SiNW GAA with small triangular cross sections, a single-electron transistor (SET) operation regime is highlighted at T = 5 K This is attributed to a combined effect of strain and corner conduction in triangular channel cross sections, suggesting the possibility to hybridize CMOS and SET functions by a unique nanowire fabrication platform

Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon

The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications [2]. Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA) [3,4]. Unfortunately in all cases a relatively large average SS and a poor on-current have been observed.

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices.

/pdf/the-high-mobility-bended-n-channel-silicon-nanowire-bu1s9htkat.pdf

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

In this paper we investigate the mobility enhancement due to strain in bended NW MOSFETs. Stress of 200 MPa to 2 GPa, induced by thermal oxidation, is measured in suspended NW FETs by Raman spectroscopy. Mobility enhancement of more than 100% is observed. Performance gain of bended compared to non-bended structures is most pronounced in low field conditions and at low temperatures.

L. De Michielis

Papers

Understanding the Superlinear Onset of Tunnel-FET Output Characteristic

Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

Bended Gate-All-Around Nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress