scispace - formally typeset
Search or ask a question
Author

L.J. McDaid

Bio: L.J. McDaid is an academic researcher from University of Liverpool. The author has contributed to research in topics: Silicon on insulator & Field-effect transistor. The author has an hindex of 7, co-authored 19 publications receiving 210 citations.

Papers
More filters
Journal ArticleDOI
TL;DR: In this article, it was shown that a significant increase in temperature occurs in the channel of SOI transistors due to the relatively poor thermal conductivity of the buried insulator.
Abstract: From a two-dimensional solution of Laplace's equation it is shown that a significant increase in temperature occurs in the channel of SOI transistors due to the relatively poor thermal conductivity of the buried insulator. Based on this simulation an equation is derived which predicts that at small channel lengths the pinchoft point is shifted, an effect which is consistent with experimental observations. In addition, the positive 'kink' is reduced with increasing gate voltage and this effect, together with the negative differential resistance, can be explained by a temperature increase in the channel.

109 citations

Journal ArticleDOI
TL;DR: In this paper, it is demonstrated that from a single high frequency capacitance-voltage (C-V) plot performed on an SOI capacitor, one can obtain the buried insulator and body (active layer) thickness.
Abstract: To predict the performance of SOI transistors, it is essential that material dimensions and parameters are accurately known. It is demonstrated here that from a single high frequency capacitance-voltage (C-V) plot performed on an SOI capacitor, one can obtain the buried insulator and body (active layer) thickness. The results obtained from the method are verified by independent C-V measurements carried out on the same device. In the present case this technique is demonstrated using SIMOX material but applies equally well to other SOI technologies. Because of the ease of fabrication of the capacitor such a measurement can be performed on starting material. The measurement strictly applies to the condition of a fully depleted body, but in the partially depleted case the thickness of the buried oxide can still be estimated.

21 citations

Proceedings ArticleDOI
01 Oct 1991
TL;DR: In this article, the peak temperature rise due to self-heating in the silicon body of an n-channel transistor was measured by monitoring the leakage current as a function of the maximum power density.
Abstract: The peak temperature rise due to self-heating in the silicon body of an n-channel transistor was measured by monitoring the leakage current as a function of the maximum power density. The transistors were fabricated using SIMOX technology where the equivalent of 1.8*10/sup 18/ O/sup +/ ions/cm/sup 2/ were implanted at an energy of 200 keV followed by an anneal at 1300 degrees C for 6 h. The technique requires a contact to the body region with which to monitor the leakage currents. A significant temperature rise is observed for low power densities. The advantage of this techinque is that peak temperature rise is measured in an actual transistor from a simple measurement and analysis. Furthermore, the enhanced leakage current, which the technique measures, provides an additional source of base current for the parasitic lateral bipolar transistor. >

20 citations

Journal ArticleDOI
TL;DR: In this paper, it was demonstrated that silicidation of the source region in a silicon-on-insulator MOSFET can improve the parasitic bipolar induced breakdown voltage to beyond 5 V.
Abstract: It is demonstrated that silicidation of the source region in a silicon-on-insulator MOSFET can improve the parasitic bipolar induced breakdown voltage to beyond 5 V. The technique results in a degradation of the parasitic bipolar current gain by increasing the minority carrier current across the source body junction, thereby causing a reduction in the emitter efficiency. Silicidation of both the source and drain regions is performed simultaneously thus maintaining device symmetry and simplicity of processing. No significant degradation of drain leakage leakage current was observed.

12 citations

Journal ArticleDOI
TL;DR: Experimental results indicate that STDP with biologically plausible critical timing windows over the range from [email protected]?s to 100ms can be implemented and a floating gate weight storage capability, with drive circuits, is presented.

11 citations


Cited by
More filters
Journal ArticleDOI
TL;DR: In this article, the authors measured and modeled self-heating in SOI nMOSFETs under static operating conditions and showed that the measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation.
Abstract: Self-heating in SOI nMOSFET's is measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation. Under dynamic circuit conditions, the channel temperatures are much lower than predicted from the static power dissipation. This work provides the foundation for the extraction of device modeling parameters for dynamic operation (at constant temperature) from static device characterization data (where temperature varies widely). Self-heating does not greatly reduce the electromigration reliability of SOI circuits, but might influence SOI device design, e.g., requiring a thinner buried oxide layer for particular applications and scaled geometries. >

312 citations

Journal ArticleDOI
TL;DR: In this article, a new thermal extraction technique based on an analytically derived expression for the electro-thermal drain conductance in saturation is presented, which can be used confidently over a wide range of bias conditions, with both fully and partially depleted devices.
Abstract: Self-heating is an important issue for SOI CMOS, and hence, so is its characterization and modeling. This paper sets out how the critical parameters for modeling, i.e., thermal resistance and thermal time-constants, may be obtained using purely electrical measurements on standard MOS devices. A summary of the circuit level issues is presented, and the physical effects contributing to thermally related MOSFET behavior are discussed. A new thermal extraction technique is presented, based on an analytically derived expression for the electro-thermal drain conductance in saturation. Uniquely, standard MOSFET structures can be used, eliminating errors due to additional heat flow through special layouts. The conductance technique is tested experimentally and results are shown to be in excellent agreement with thermal resistance values obtained from noise thermometry and gate resistance measurements using identical devices. It is demonstrated that the conductance technique can be used confidently over a wide range of bias conditions, with both fully and partially depleted devices.

199 citations

Journal ArticleDOI
TL;DR: In this article, the vertical thermal conductivities of thermally grown (TG) and chemical vapor deposited (CVD) silicon dioxide layers 20 to 200 nm thick were measured using a simple, noncontact photothermal technique.
Abstract: The vertical thermal conductivities of thermally grown (TG) and chemical vapor deposited (CVD) silicon‐dioxide layers 20 to 200 nm thick are measured using a simple, noncontact photothermal technique. The conductivities of TG and CVD layers are less by as much as 18% and 30%, respectively, than the conductivity of bulk fused silicon dioxide. No significant thickness dependence is observed. The thermal boundary resistance between the oxide layers and silicon is shown to be negligibly small. The boundary resistance of gold layers sputtered directly onto TG oxide is considerably larger than that of gold layers evaporated on TG oxide with a 20‐nm chromium adhesion layer, and is comparable to internal resistances of the oxide layers.

180 citations

Journal ArticleDOI
TL;DR: In this article, the formation of nickel mono-silicide (NiSi) using rapid thermal annealing, the thermal stability of NiSi on n+ poly-Si and the contact resistance on n + Si layers in a SIMOX structure were investigated.
Abstract: Self-aligned silicidation is a well-known process to reduce source, drain, and gate resistances of submicron metal-oxide-semiconductor devices. This process is particularly useful for devices built on very thin Si layers (∼1000 A or less) on insulators because of the large source and drain resistances associated with the thin Si layer. NiSi is a good candidate for salicidation process due to its low resistivity, low formation temperature, little silicon consumption, and large stable processing temperature window. In this article, the formation of nickel mono-silicide (NiSi) using rapid thermal annealing, the thermal stability of NiSi on n+ poly-Si and the contact resistance of NiSi on n+ Si layers in a SIMOX structure were investigated. NiSi salicidation process was, then, incorporated into a NMOS/SIMOX device fabrication for partial and full consumption of the Si in the source and drain regions during the salicidation process. The effects of void formation and silicide encroachment on the device performa...

163 citations

Patent
07 May 2009
TL;DR: In this article, a method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by a manufacturing process and a second set are variable.
Abstract: A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing process and a second set are variable, said second set comprising at least a fin width (W fin ), a gate length (L G ) and a number of fins (N) of said MuGFET ESD protection device, said second set further comprising a subset of at least one other parameter which depends on said fin width (W fin ), gate length (L G ) and number of fins (N). The method comprises the following steps: (a) selecting multiple combinations of possible values which meet predetermined ESD constraints; (b) determining multiple values for said subset on the basis of a predetermined relationship; (c) determining for said subset an optimum value in view of a predetermined design target; (d) determining values for said fin width (W fin ), gate length (L G ) and number of fins (N) on the basis of the/each optimum value; (e) manufacturing said MuGFET ESD protection device using said given manufacturing process and said values determined in step d).

142 citations