L. K. Bera

Bio: L. K. Bera is an academic researcher from Singapore Science Park. The author has contributed to research in topics: MOSFET & Time-dependent gate oxide breakdown. The author has an hindex of 8, co-authored 11 publications receiving 284 citations.

Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance

Abstract: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well

Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs

Abstract: A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current. Vertical stacking economizes on silicon estate and improves the on-state IDSAT at the same time. Both n- and p-FET devices are demonstrated

A comprehensive model for breakdown mechanism in HfO/sub 2/ high-k gate stacks

Abstract: Based on physical analysis results, a model describing the breakdown (BD) mechanism of HfO/sub 2//polysilicon gate stack is proposed. Due to the high mechanical strength and the polycrystalline nature of annealed HfO/sub 2/ dielectrics, and a very complicated BD induced thermo-chemical reaction and self-healing process, the BD mechanism and transient evolution in HfO/sub 2/ gate stacks are different from that of ultrathin SiO/sub x/N/sub y/. The formation of a percolation path is probably assisted by grain boundaries and/or enhanced electric field strength near the poly-Si edge. Besides polarity-dependent dielectric-BD-induced epitaxy (DBIE), due to the BD induced thermo-chemical reactions among HfO/sub 2/, SiO/sub x/ (i.e. IL oxide), Hf-compounds and Si, the formation of a dielectric-based "clog" which is HfSi/sub x/ O/sub y/-rich, termed as dielectric-BD-induced self-healing insulating cap (SHIC), is proposed. The microstructures of DBIE and SHIC are responsible for the leakage current evolution during a BD event in HfO/sub 2/ gate stacks.

Ultrafast progressive breakdown associated with metal-like filament formation of a breakdown path in a HfO2∕TaN∕TiN transistor

Abstract: Ultrafast progressive breakdown has been observed in a TaN∕TiN metal gate metal-oxide-semiconductor field effect transistor (MOSFET) compared to a polycrystalline silicon gate MOSFET. Physical analysis by transmission electron microscopy and electrical characterization shows that the ultrafast progressive breakdown is likely to be associated with a metal-like filament formation of the breakdown path. It has been observed that the metal-like filament of the breakdown path is detrimental to the metal gate MOSFET progressive breakdown lifetime.

Substrate injection induced ultrafast degradation in HfO2/TaN/TiN gate stack MOSFET

Abstract: HfO2 high-?/TaN/TiN gate stacks n/p-MOSFETs have been studied. Ultrafast progressive breakdown (PBD) is polarity dependent and is found only in the case of substrate injection in metal gate n/p-MOSFETs. PBD transient of metal gate p-MOSFET is much slower than n-MOSFET in inversion mode stress.

Carbon Nanotubes for High-Performance Electronics—Progress and Prospect

Abstract: Carbon nanotube devices offer intrinsic advantages for high-performance logic device applications. The ultrasmall body of a carbon nanotube-the tube diameter-is the key feature that should allow aggressive channel length scaling, while the intrinsic transport properties of the nanotube ensure at the same time high on-currents. In addition, the narrowness of the tube is critical to implementation of novel device concepts like the tunneling transistor. By understanding the unique capabilities of carbon nanotubes and using them in unconventional designs, novel nanoelectronic applications may become feasible. However, much better control of materials quality must be obtained, and new fabrication processes must be developed before such applications can be realized.

Bandstructure Effects in Silicon Nanowire Electron Transport

Abstract: Bandstructure effects in the electronic transport of strongly quantized silicon nanowire field-effect-transistors (FET) in various transport orientations are examined. A 10-band sp3d5s* semiempirical atomistic tight-binding model coupled to a self-consistent Poisson solver is used for the dispersion calculation. A semi-classical, ballistic FET model is used to evaluate the current-voltage characteristics. It is found that the total gate capacitance is degraded from the oxide capacitance value by 30% for wires in all the considered transport orientations ([100], [110], [111]). Different wire directions primarily influence the carrier velocities, which mainly determine the relative performance differences, while the total charge difference is weakly affected. The velocities depend on the effective mass and degeneracy of the dispersions. The [110] and secondly the [100] oriented 3 nm thick nanowires examined, indicate the best ON-current performance compared to [111] wires. The dispersion features are strong functions of quantization. Effects such as valley splitting can lift the degeneracies particularly for wires with cross section sides below 3 nm. The effective masses also change significantly with quantization, and change differently for different transport orientations. For the cases of [100] and [111] wires the masses increase with quantization, however, in the [110] case, the mass decreases. The mass variations can be explained from the non-parabolicities and anisotropies that reside in the first Brillouin zone of silicon.

Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications

Abstract: Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits.

Abstract: We introduce the concept of a silicon nanotube field effect transistor whose unique core–shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core–shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow.

Scaling of Nanowire Transistors

Abstract: This paper considers the scaling of nanowire transistors to 10-nm gate lengths and below. The 2-D scale length theory for a cylindrical surrounding-gate MOSFET is reviewed first, yielding a general guideline between the gate length and the nanowire size for acceptable short-channel effects. Quantum confinement of electrons in the nanowire is discussed next. It gives rise to a ground-state energy and, therefore, a threshold voltage dependent on the radius of the nanowire. The scaling limit of nanowire transistors hinges on how precise the nanowire size can be controlled. The performance limit of a nanowire transistor is then assessed by applying a ballistic current model. Key issues such as the density of states of the nanowire material are discussed. Comparisons are made between the model results and the published experimental data of nanowire devices.