This paper presents a CMOS imager with a column-parallel ADC architecture based on a multiple-ramp single-slope (MRSS) ADC. Like the well-known column-level single-slope ADC, an MRSS ADC uses a very simple analog column circuit, which mainly consists of an analog comparator and some switches. A prototype imager using the MRSS ADC architecture was realized in a 0.25 CMOS process. Measurements demonstrate that the conversion speed of an MRSS ADC is 3.3 higher than a single-slope ADC while dissipating only 16% more power. Furthermore, the MRSS ADC can be easily adapted to exhibit a companding characteristic, which exploits the amplitude-dependent nature of the photon shot noise present in imager signals. Measurements show that the resulting multiple-ramp multiple-slope ADC is 25% faster than an MRSS ADC while dissipating the same amount of power.

Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors

This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 times 240 pixels has been fabricated with a 0.35-mum CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 mus , which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of +0.53/ -0.78 LSB and INL of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.

A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs

Many mixed-signal circuits are nonlinear time-varying systems whose noise estimation cannot be obtained from the conventional frequency domain noise simulation (FNS). Although the transient noise simulation (TNS) supported by a commercial simulator takes into account nonlinear time-varying characteristics of the circuit, its simulation time is unacceptably long to obtain meaningful noise estimation results. Since the single-slope analog-to-digital converter with correlated double sampling (CDS/SS-ADC) in a CMOS image sensor (CIS) is composed of several operation phases in which the circuit topologies are different from each other, the noise cannot be estimated by the conventional FNS. This paper presents a noise estimation method for the CDS/SS-ADC that uses the FNS results while the transient noise behavior is taken into account. The proposed method provides noise estimation results closer to that of the TNS than the conventional FNS, whereas the simulation time is about the same as that of the FNS.

Noise Analysis and Simulation Method for a Single-Slope ADC With CDS in a CMOS Image Sensor

This paper proposes a column-parallel two-step single-slope analog-to-digital converter (SS ADC) for high-frame-rate CMOS image sensors. The proposed two-step SS ADC circuit does not utilize an analog memory capacitor to store the value of the first ramp step. Instead, to handle problems such as the slope errors of the second ramp and the stored charge error from charge feed-through, it utilizes a very simple digital column circuit consisting of a coarse counter (coarse step counter) and a 4-to-16 decoder. The second ramp (fine ramp) slope has only one slope generator, regardless of the results of the first ramp decisions, to eliminate the slope mismatch between fine ramp slopes. A prototype sensor comprising 640 $\times$ 480 pixels was fabricated with a 0.13- $\mu{\rm m}$ CMOS process. The results of experiments conducted indicate that the proposed ADC can achieve a conversion time of 6.4 $\mu{\rm s}$ at a main clock frequency of 62.5 MHz, which is 10.2 times faster than the conventional SS ADC. The maximum frame rate of the proposed VGA CMOS Image Sensor (CIS) is 320 frames per second (fps). Further, the proposed circuit employs redundancy error correction logic to calibrate the error between the coarse and fine steps. The total power consumption is 72 mW from supply voltages of 2.8 V (analog) and 1.5 V (digital). The figure of merit (FoM) of the proposed VGA CMOS image sensor is 2.01 $[e^{-}\ {\rm nJ}]$ .

High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs

This paper presents a 4K2K 480-fps global-shutter CMOS image sensor with a super 35-mm format for a highly realistic digital video system. The sensor employs newly developed gain-adaptive column analog-to-digital converters to obtain input-referred dark random noise of 140 $\mu \text{V}_{\mathrm {rms}}$ for an input-referred full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintained the nonlinearity of the output image within 0.18%. A chip-on-chip integration process realized a front-illuminated image sensor stacked with two diced logic chips through 38-K microbump interconnections. The global-shutter pixel achieved a parasitic light sensitivity of −99.6 dB. The 16-channel output interfaces with 4.752 Gbps/ch were implemented in the stacked logic chips.

8.3 M-Pixel 480-fps Global-Shutter CMOS Image Sensor with Gain-Adaptive Column ADCs and Chip-on-Chip Stacked Integration

This brief presents a new simultaneous multislope analog-digital converter (ADC) architecture suitable for array implementations in, e.g., CMOS image sensors (CISs). The simplest implementation is almost twice as fast as a conventional-slope ADC, while it requires only a small amount of extra circuitry. Measurements have been performed on a custom made CIS which implements parts of the proposed ADC. The measurements show good linearity and verify the concept of the new architecture

L. Lindgren

Papers

A New Simultaneous Multislope ADC Architecture for Array Implementations