L Lorenz

Bio: L Lorenz is an academic researcher. The author has contributed to research in topics: High voltage. The author has an hindex of 1, co-authored 1 publications receiving 115 citations.

State-of-the-art, single-phase, active power-factor-correction techniques for high-power applications - an overview

Abstract: A review of high-performance, state-of-the-art, active power-factor-correction (PFC) techniques for high-power, single-phase applications is presented. The merits and limitations of several PFC techniques that are used in today's network-server and telecom power supplies to maximize their conversion efficiencies are discussed. These techniques include various zero-voltage-switching and zero-current-switching, active-snubber approaches employed to reduce reverse-recovery-related switching losses, as well as techniques for the minimization of the conduction losses. Finally, the effect of recent advancements in semiconductor technology, primarily silicon-carbide technology, on the performance and design considerations of PFC converters is discussed.

The future of power semiconductor device technology

Abstract: Power electronic systems have benefited greatly during the past ten years from the revolutionary advances that have occurred in power discrete devices. The introduction of power metal-oxide-semiconductor field-effect transistors (MOSFETs) in the 1970s and the insulated gate bipolar transistors (IGBTs) in the 1980s enabled design of very compact high-efficiency systems due to the greatly enhanced power gain resulting from the high input impedance of these structures. Recently, significant improvements in the performance of silicon-power MOSFETs has been achieved by using innovative vertical structures with charge coupled regions. Meanwhile, silicon IGBTs continue to dominate the medium- and high-voltage application space sue to scaling of their voltage ratings and refinements to their gate structure achieved by using very large scale integration (VLSI) technology and trench gate regions. Research on a variety of MOS-gated thyristors has also been conducted, resulting in some promising improvements in the tradeoff between on-state power loss, switching power loss, and the safe-operating-area. Concurrent improvements in power rectifiers have been achieved at low-voltage ratings using Schottky rectifier structures containing trenches and at high-voltage ratings using structures that combine junction and Schottky barrier contacts. On the longer term, silicon carbide Schottky rectifiers and power MOSFETs offer at least another tenfold improvement in performance. Although the projected performance enhancements have been experimentally demonstrated, the defect density and cost of the starting material are determining the pace of commercialization of this technology at present.

Gate drive design considerations for high voltage cascode GaN HEMT

Abstract: This paper investigates gate drive design for high voltage gallium nitride (GaN) high electron-mobility transistors (HEMT) in a cascade structure. High dv/dt and di/dt switching characteristics of GaN device and its influences on high-side gate drive are analyzed on an 8.4kW bidirectional multi-channel buck/boost battery charger operating in critical conduction mode (CRM). Driving candidates for high-side gate drive are reviewed, and digital isolator based driving architecture is proposed with discussion of PCB layout and package parasitics. Experimental results are conducted in each step for concepts validation.

A power mosfet having laterally three-layered structure formed among element isolation regions

Abstract: A semiconductor apparatus has an NPN (or PNP) laterally three-layered pillar formed in a mesh form among a plurality of trench type element isolation regions, and having a source and gate on an upper surface of the three-layered pillar, and a drain on a lower surface thereof. A depth DT and minimum planar width WTmin of the element isolation region and a width WP of the three-layered pillar are configured to satisfy a relation of 3.75≦DT/WP≦60 or 5.5≦DT/WTmin≦14.3. The above configuration realizes a high breakdown voltage and low on-resistance are realized.

Matched pair of CoolMOST/sup TM/ transistor with SiC-Schottky diode-advantages in application

Abstract: The new CoolMOS C3 generation combines extremely high on-state conductivity with ultrafast switching speed at full pulse current capability. In the first generation of CoolMOS the saturation current was intentionally reduced at the cell level for the benefit of short-circuit ruggedness. This technique results in a reduced current capability of the device at low gate voltages, which has been overcome today by the C3 family. In some applications the outstanding switching performance of the CoolMOS cannot be utilized due to the dynamic behavior of the diode. For this reason a whole family of SiC diodes has been developed to attain the ideal matched pair of switch and ultrafast diodes. The goal of ultralow-loss applications in switched mode power supplies, power factor correction circuits, and motor control units will be achieved perfectly.