Laavanya Sridhar

Bio: Laavanya Sridhar is an academic researcher. The author has contributed to research in topics: Field-programmable gate array & Control reconfiguration. The author has an hindex of 1, co-authored 2 publications receiving 5 citations.

RFID based access control protection scheme for SRAM FPGA IP cores

Abstract: Field-programmable gate-array (FPGA) based hardware IP cores have emerged as an integral part of modern SOC designs. IP trading plays central role in Electronic Design Automation (EDA) industry. While the potential of IP infringement is growing fast, the global awareness of IP protection remains low. In this work, we propose a Radio Frequency Identification (RFID) based protection scheme for Intellectual Property Protection (IPP) of Static Random Access Memory (SRAM) FPGA IP cores that overcome the limitations of existing IPP techniques. Here, three types of reconfigurable RFID tags is realised in order to support the incorporation of the proposed RFID based security scheme in all the reconfigurable FPGA devices of Xilinx family. Also a special tag bypass feature is employed to increase the suitability of proposed scheme as an IPP technique for reconfigurable IP cores. The proposed scheme supports safe exchange of reconfigurable FPGA IP cores between IP providers and system developers. The results derived from the testing of hardware prototype used for the evaluation of the proposed scheme are quite encouraging and shows that the proposed security feature can be incorporated into the reconfigurable IP cores of any functionality without significant performance degradation of the reconfigurable IP cores.

RF authenticated reconfiguration-based access control protection scheme for SRAM-based FPGA IP cores

Abstract: The constantly growing demand for ready to use design components, also known as intellectual property IP cores, has created a very lucrative and flourishing market which is very likely to continue its current path not only into the near future. With increase in use of field programmable gate arrays FPGAs in production designs, and with growth of system on FPGA SOF applications, the security of FPGA IP cores cannot be taken for granted anymore. In this paper, we have proposed a novel wireless-based IP core infringement preventive approach for intellectual property protection IPP of static random access memory SRAM-based FPGA IP cores. The proposed scheme exploits reconfiguration aspect of SRAM-based FPGA and incorporates special tag bypass features for increase suitability of proposed scheme as an IPP technique for reconfigurable IP cores. A hardware prototype is developed for evaluation of proposed scheme and the testing results are quite encouraging.

Exploring DWT-SVD-DCT feature parameters for robust multiple watermarking against JPEG and JPEG2000 compression

Abstract: Display Omitted A blind image watermarking scheme exploiting the DWT-SVD-DCT features is presented.The proposed PQIM reaches a trade-off between robustness and imperceptibility.Multiple watermarks can be embedded into a host image.The watermarks exhibit exceptional robustness against JPEG and JPEG2000 compression. This paper presents a novel scheme to implement blind image watermarking based on the feature parameters extracted from a composite domain including the discrete wavelet transform (DWT), singular value decomposition (SVD), and discrete cosine transform (DCT). Multiple bits can be embedded into a single image block by adjusting designated parameters via a progressive quantization index modulation technique. The quantization with respect to the feature parameters obtained in the DWT-SVD-DCT domain leads to efficient watermark extraction without referring to the original image. Experimental results show that the embedded watermarks exhibit exceptional robustness against image compression using JPEG and JPEG2000 coding standards.

RFID-Enabled Physical Object Tracking in Process Flow Based on an Enhanced Graphical Deduction Modeling Method

Abstract: The purpose of this paper is to develop an enhanced radio frequency identification (RFID)-enabled graphical deduction model (rfid-GDM) for tracking the time-sensitive state, position, and other attributes of RFID-tagged objects in process flow. Concepts and definitions related to processes and RFID applications are first clarified, and enhanced state blocks are proposed to depict four kinds of RFID application scenarios. The implementation framework of rfid-GDM and its five steps are further addressed. Both mathematical formalization and graphical description of each step are involved. Finally, a case is studied to verify the feasibility of rfid-GDM. It is expected that rfid-GDM will provide instructions for modeling and tracking RFID-enabled process flows in diverse fields.

Hardware Activation by Means of PUFs and Elliptic Curve Cryptography in Field-Programmable Devices

Abstract: Reusable design using IP cores requires of efficient methods for protecting the Intellectual Property of the designer and the corresponding license agreements. In this work, a new protection procedure establishing an activation protocol in a similar way to the activation process in the software world is presented. The procedure, named SEHAS (Secure Hardware Activation System) allows the distribution of cores in either Blocked (not functioning) or Demo (functioning with limited features) modes, while ensuring the license agreements by identifying not only the IP core but also the implementation device, using Physically Unclonable Functions (PUF). Moreover, SEHAS secures the exchange of information between the core and the core vendor using an Elliptic Curve Cryptosystem (ECC). This secure channel allows the IP core vendor to send a unique Activation Code to the core in order to switch it to the Activated Mode, thus enabling all its features.

Improvements for the applicability of power-watermarking to embedded IP cores protection

Abstract: The intellectual property protection of deliverable cores is a major challenge for the design of digital systems based on reusable modules. Usually, the existing protection procedures introduce a digital signature identifying the authorship into the core under protection, which must be recovered later for verification purposes. The recovery of the signature is particularly difficult when the Intellectual Property (IP) cores are embedded into complex systems, without direct access to the input/output pins. In the present paper, improved techniques based on power watermarking for introducing and extracting a digital signature from embedded cores are presented, providing a complete framework for the protection of IP cores. Moreover, the protection module can accommodate part of the combinational logic of the core under protection, causing malfunction of the system if the protection is removed. Experimental results and several design examples show the suitability and robustness of the proposed methods.

RFID, Social Sensors and Extended Cyber-Physical System

Abstract: In this chapter, the roles of RFID, social sensors, and cyber-physical system (CPS) at both inter-enterprise level and intra-enterprise level under the context of social manufacturing are elaborated. Advanced IoT solutions, human-machine interaction technologies and manufacturing data analysis enable humans, machines, sensors, smart workpieces and software systems to interact and cooperate with each other simultaneously for production operations. Firstly, an RFID-based graphical deduction model is constructed for tracing and monitoring material flows. Then, the concept, operational logic and implementation methods of social sensors are discussed in detail. Finally, an extended CPS framework integrating with RFID and social sensors is proposed to power social manufacturing nodes, communities, and network for production tasks. Potential application prospects of social manufacturing are also introduced from technical integration and application perspectives.