Lakshmi Kanta Bera

Bio: Lakshmi Kanta Bera is an academic researcher from Agency for Science, Technology and Research. The author has contributed to research in topics: High-electron-mobility transistor & Schottky barrier. The author has an hindex of 15, co-authored 58 publications receiving 1672 citations. Previous affiliations of Lakshmi Kanta Bera include Indian Institute of Technology Kharagpur.

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

Abstract: This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

Stacked silicon-germanium nanowire structure and method of forming the same

Abstract: A method of forming a stacked silicon-germanium nanowire structure on a support substrate is disclosed. The method includes forming a stacked structure on the support substrate, the stacked structure comprising at least one channel layer and at least one interchannel layer deposited on the channel layer; forming a fin structure from the stacked structure, the fin structure comprising at least two supporting portions and a fin portion arranged there between; oxidizing the fin portion of the fin structure thereby forming the silicon-germanium nanowire being surrounded by a layer of oxide; and removing the layer of oxide to form the silicon-germanium nanowire. A method of forming a gate-all-around transistor comprising forming a stacked silicon-germanium nanowire structure that has been formed on a support substrate is also disclosed. A stacked silicon-germanium nanowire structure and a gate-all-around transistor comprising the stacked silicon-germanium nanowire structure are also disclosed.

Strained-Si heterostructure field effect transistors

Abstract: The purpose of this review article is to report on the recent developments and the performance level achieved in the strained-Si/SiGe material system. In the first part, the technology of the growth of a high-quality strained-Si layer on a relaxed, linear or step-graded SiGe buffer layer is reviewed. Characterization results of strained-Si films obtained with secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy, spectroscopic ellipsometry and Raman spectroscopy are presented. Techniques for the determination of bandgap parameters from electrical characterization of metal-oxide-semiconductor (MOS) structures on strained-Si film are discussed. In the second part, processing issues of strained-Si films in conventional Si technology with low thermal budget are critically reviewed. Thermal and low-temperature microwave plasma oxidation and nitridation of strained-Si layers are discussed. Some recent results on contact metallization of strained-Si using Ti and Pt are presented. In the last part, device applications of strained Si with special emphasis on heterostructure metal oxide semiconductor field effect transistors and modulation-doped field effect transistors are discussed. Design aspects and simulation results of n- and p-MOS devices with a strained-Si channel are presented. Possible future applications of strained-Si/SiGe in high-performance SiGe CMOS technology are indicated.

AlGaN/GaN two-dimensional-electron gas heterostructures on 200 mm diameter Si(111)

Abstract: This Letter reports on the epitaxial growth, characterization, and device characteristics of crack-free AlGaN/GaN heterostructures on a 200 mm diameter Si(111) substrate. The total nitride stack thickness of the sample grown by the metal-organic chemical vapor deposition technique is about 3.3 ± 0.1 μm. The structural and optical properties of these layers are studied by cross-sectional scanning transmission electron microscopy, high-resolution x-ray diffraction, photoluminescence, and micro-Raman spectroscopy techniques. The top AlGaN/GaN heterointerfaces reveal the formation of a two-dimensional electron gas with average Hall mobility values in the range of 1800 to 1900 cm2/Vs across such 200 mm diameter GaN on Si(111) samples. The fabricated 1.5 μm-gate AlGaN/GaN high-electron-mobility transistors exhibited the drain current density of 660 mA/mm and extrinsic transconductance of 210 mS/mm. These experimental results show immense potential of 200-mm diameter GaN-on-silicon technology for electronic devi...

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

Abstract: We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around nand p-FETs, fabricated using these stacked NW arrays as the channel (Lgges0.35 mum), exhibit excellent device performance with high ION/IOFF ratio (~106), near ideal subthreshold slope (~62-75 mV/dec) and low drain induced barrier-lowering (~20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

Abstract: This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...

25th Anniversary Article: Semiconductor Nanowires – Synthesis, Characterization, and Applications

Abstract: Semiconductor nanowires (NWs) have been studied extensively for over two decades for their novel electronic, photonic, thermal, electrochemical and mechanical properties. This comprehensive review article summarizes major advances in the synthesis, characterization, and application of these materials in the past decade. Developments in the understanding of the fundamental principles of "bottom-up" growth mechanisms are presented, with an emphasis on rational control of the morphology, stoichiometry, and crystal structure of the materials. This is followed by a discussion of the application of nanowires in i) electronic, ii) sensor, iii) photonic, iv) thermoelectric, v) photovoltaic, vi) photoelectrochemical, vii) battery, viii) mechanical, and ix) biological applications. Throughout the discussion, a detailed explanation of the unique properties associated with the one-dimensional nanowire geometry will be presented, and the benefits of these properties for the various applications will be highlighted. The review concludes with a brief perspective on future research directions, and remaining barriers which must be overcome for the successful commercial application of these technologies.

A 90-nm logic technology featuring strained-silicon

Abstract: A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.

Semiconductor device and method of fabricating the same

Abstract: A method of fabricating a semiconductor device includes following steps. A substrate is provided, wherein a first dielectric layer having a trench therein is formed on the substrate, a source/drain region is formed in the substrate at two sides of the trench, and a second dielectric layer is formed on the substrate in the trench. A first physical vapor deposition process is performed to form a Ti-containing metal layer in the trench. A second physical vapor deposition process is performed to form an Al layer on the Ti-containing metal layer in the trench. A thermal process is performed to anneal the Ti-containing metal layer and the Al layer so as to form a work function metal layer. A metal layer is formed to fill the trench.