Lan Nan

Bio: Lan Nan is an academic researcher from National University of Singapore. The author has contributed to research in topics: CMOS & Microstrip. The author has an hindex of 10, co-authored 24 publications receiving 337 citations. Previous affiliations of Lan Nan include Agency for Science, Technology and Research & University of California, Los Angeles.

Design of 60- and 77-GHz Narrow-Bandpass Filters in CMOS Technology

Abstract: This paper investigates the design and implementation of millimeter-wave narrow-bandpass filters in a standard 0.18- m CMOS technology. Filters with a measured 10% 3-dB bandwidth at 60 and 77 GHz are realized in a thin-film microstrip structure by using the lowest metallization layer as a ground plane. The impact of dissipation losses of the filters is also examined. It is found that the metallization losses in the coupled-line filter as well as the ground plane are the main reasons for the insertion loss.

High-Speed mm-Wave Data-Link Based on Hollow Plastic Cable and CMOS Transceiver

Abstract: A multi-Giga-bit/s (up to 6 Gbps) and energy-efficient (1 pJ/bit/m) data link is formed by using hollow plastic cable and CMOS transceivers for short distance (8 m) digital communications. The demonstrated link couples/de-couples 60 GHz carried digital signals with roughly 6 dB loss per coupling into/from a hollow plastic cable made of relatively low-loss (~1.5 dB/m) Teflon, which is widely used for various home appliances. The CMOS transceivers are designed and implemented in 65 nm Foundry CMOS to support the intended 60 GHz operation with 28 mW power consumption under a 1 V supply.

Experimental Characterization of the Effect of Metal Dummy Fills on Spiral Inductors

Abstract: In modern CMOS technologies, metal dummy fills are required to maintain metal density uniformity and to planarize the layers. As frequency increases, the effect of the metal dummy fills on the CMOS integrated circuits or components should be taken into account. This work presents experimental results of the effect of metal dummy fills on the microwave behavior of spiral inductors fabricated in a standard 0.18-mum CMOS technology. The influences on the equivalent model parameters and the Q-factor are characterized based on measured S-parameters of inductors with and without metal dummy fills.

A Wideband Scalable and SPICE-Compatible Model for On-Chip Interconnects Up to 110 GHz

Abstract: A fully scalable and SPICE compatible wideband model of on-chip interconnects valid up to 110 GHz is presented in this paper. The series branches of the proposed multisegment model consist of an RL ladder network to capture the skin and proximity effects, as well as the substrate skin effect. Their values are obtained from a technique based on a modified effective loop inductance approach and complex image method. A CG network is used in the shunt branches of the model, which accounts for capacitive coupling through the oxide and substrate loss due to the electrical field, as well as the impact of dummy metal fills. The values of these elements are determined by analytical and semiempirical formulas. The model is validated by a full-wave electromagnetic field solver, as well as measurements. The simulated S-parameters of the model agree well with the measured S-parameters of on-chip interconnects with different widths and lengths over a wide frequency range from dc up to 110 GHz.

A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines

Abstract: The expanding capacity of today's memory cards and increasing speed of processors have created demands for high data rate interfaces between memory cards and processors. Compared to conventional contact pins, wireless interfaces have received tremendous interest for reasons of more convenience, higher reliability, and higher data rate. Two major types of near-field wireless communication techniques using capacitive coupling and inductive coupling channels have been investigated. Tens of Gb/s/ch is achieved using both methods with a communication distance of tens of microns in TCI (thru-chip-interface) applications [1–2]. However, when the communication distance denters the mm range in such applications as non-contact memory cards, the sizes of capacitors or inductors must be up scaled to detect enough electrical flux or magnetic flux, whose magnitude decay as 1/dn (n>1). As a result, the self-resonance frequency f SR is reduced significantly, which becomes the dominant limiting factor for the achievable data rate, since the maximum data rate is usually chosen as 1/2 or 1/3 of f SR in order to avoid signal peaking [3]. Although multi-channel solutions are viable to increase the total data rate, complex systems are required to address the skew issues in synchronization, and low area efficiency is resulted to reduce crosstalk interferences as shown in Fig. 28.3.1.

A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS

Abstract: A 60-GHz dual-mode power amplifier (PA) is implemented in 40-nm bulk CMOS technology. To boost the amplifier performance at millimeter-wave (mmWave) frequencies, a new transistor layout is proposed to minimize the device and interconnect parasitics while the neutralized amplifier stage is co-optimized with input transformer to improve the power gain and stability. The transformer-based power-combining PA consists of two unit amplifiers, operating in Class AB for better back-off efficiency. To further reduce the power consumption and hence extend battery lifetime, one unit PA is tuned off in low-power mode. A switch is used to short the output of this non-operating unit PA to reduce the combiner loss and improve the efficiency. The PA achieves a measured saturated output power (PSAT) of 17.0 dBm (12.1 dBm) and 1-dB compressed power (P1dB) of 13.8 dBm (9.1 dBm) in the high-power (low-power) mode. The power-added efficiencies (PAEs) at PSAT and P1dB are 30.3% and 21.6% respectively for the high-power mode. Compared to Class A, the PA operating in Class AB shows 5.3% improvement in measured PAE at P1dB with no compromise in linearity. The PA with the power combiner only occupies an active area of 0.074 mm 2. The reliability measurements are also conducted and the PA has an estimated lifetime of 80613 hours.

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

High-Performance Shielded Coplanar Waveguides for the Design of CMOS 60-GHz Bandpass Filters

Abstract: This paper presents optimized very high performance CMOS slow-wave shielded CPW transmission lines (S-CPW TLines). They are used to realize a 60-GHz bandpass filter, with T-junctions and open stubs. Owing to a strong slow-wave effect, the longitudinal length of the S-CPW is reduced by a factor up to 2.6 compared to a classical microstrip topology in the same technology. Moreover, the quality factor of the realized S-CPWs reaches 43 at 60 GHz, which is about two times higher than the microstrip one and corresponds to the state of the art concerning S-CPW TLines with moderate width. For a proof of concept of complex passive device realization, two millimeter-wave filters working at 60 GHz based on dual-behavior-resonator filters have been designed with these S-CPWs and measured up to 110 GHz. The measured insertion loss for the first-order (respectively, second-order) filter is -2.6 dB (respectively, -4.1 dB). The comparison with a classical microstrip topology and the state-of-the-art CMOS filter results highlights the very good performance of the realized filters in terms of unloaded quality factor. It also shows the potential of S-CPW TLines for the design of high-performance complex CMOS passive devices.

Transformer-Based Uneven Doherty Power Amplifier in 90 nm CMOS for WLAN Applications

Abstract: This paper presents a fully integrated transformer-based Doherty power amplifier in a standard 90 nm CMOS process. A novel asymmetrical series combining transformer is used to achieve uneven Doherty operation. The transformer-based uneven Doherty architecture is analyzed to further improve the back-off efficiency without linearity degradation. The fabricated two-stage uneven Doherty PA achieves a maximum output power of 26.3 dBm at 2.4 GHz with a peak power added efficiency (PAE) of 33% at 2 V supply voltage. The PAE at 6 dB back-off is still as high as 25.1%. The PA is tested with 54 Mbps WLAN 802.11g signal and it meets the stringent EVM and spectral mask requirements at 19.3 dBm average output power with a PAE of 22.9% with no need of predistortion. An open loop digital predistortion is applied to further improve the linearity. The PA satisfies WLAN requirements at 20.2 dBm average output power with a PAE of 24.7% with predistortion.

Opportunistic Feedback for Multiuser MIMO Systems With Linear Receivers

Abstract: A novel multiuser scheduling and feedback strategy for the multiple-input multiple-output (MIMO) downlink is proposed in this paper. It achieves multiuser diversity gain without substantial feedback requirements. The proposed strategy uses per-antenna scheduling at the base station, which maps each transmit antenna at the base station (equivalently, a spatial channel) to a user. Each user has a number of receive antennas that is greater than or equal to the number of transmit antennas at the base station. Zero-forcing receivers are deployed by each user to decode the transmitted data streams. In this system, the base station requires users' channel quality on each spatial channel for scheduling. An opportunistic feedback protocol is proposed to reduce the feedback requirements. The proposed protocol uses a contention channel that consists of a fixed number of feedback minislots to convey channel state information. Feedback control parameters including the channel quality threshold and the random access feedback probability are jointly adjusted to maximize the average throughput performance of this system. Multiple receive antennas at the base station are used on the feedback channel to allow decoding multiple feedback messages sent simultaneously by different users. This further reduces the bandwidth of the feedback channel. Iterative search algorithms are proposed to solve the optimization for selection of these parameters under both scenarios that the cumulative distribution functions of users are known or unknown to the base station