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Author

Lars-Ake Ragnarsson

Other affiliations: Intel, IBM, TSMC  ...read more
Bio: Lars-Ake Ragnarsson is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Metal gate & High-κ dielectric. The author has an hindex of 29, co-authored 175 publications receiving 3502 citations. Previous affiliations of Lars-Ake Ragnarsson include Intel & IBM.


Papers
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Proceedings ArticleDOI
02 May 2010
TL;DR: In this article, the similarity between Random Telegraph Noise and Negative Bias Temperature Instability (NBTI) relaxation is further demonstrated by the observation of exponentially-distributed threshold voltage shifts corresponding to single-carrier discharges in NBTI transients in deeply scaled pFETs.
Abstract: The similarity between Random Telegraph Noise and Negative Bias Temperature Instability (NBTI) relaxation is further demonstrated by the observation of exponentially-distributed threshold voltage shifts corresponding to single-carrier discharges in NBTI transients in deeply scaled pFETs. A SPICE-based simplified channel percolation model is devised to confirm this behavior. The overall device-to-device ΔV th distribution following NBTI stress is argued to be a convolution of exponential distributions of uncorrelated individual charged defects Poisson-distributed in number. An analytical description of the total NBTI threshold voltage shift distribution is derived, allowing, among other things, linking its first two moments with the average number of defects per device.

298 citations

Journal ArticleDOI
TL;DR: In this article, the authors give an overview of the challenges and issues pertaining to high-κ gate dielectric-based devices, including flat-band and threshold voltage control, carrier mobility degradation, charge trapping, gate wear-out and breakdown, and bias temperature instabilities.
Abstract: High- κ gate dielectrics like HfO 2 and HfSiO(N) are considered for the replacement of SiO 2 and SiON layers in advanced complementary metal–oxide–semiconductor (MOS) devices. Using these gate oxides allows indeed to drastically reduce the leakage current flowing through the device, as required by the specifications of the International Technology Roadmap for Semiconductors. However, major problems remain to be solved before the possible use of high- κ gate dielectrics in integrated circuits. The purpose of this paper is to give an overview of the challenges and issues pertaining to high- κ -based devices. Several issues are discussed in detail, like flat-band and threshold voltage control, carrier mobility degradation, charge trapping, gate dielectric wear-out and breakdown, and bias temperature instabilities. Our current understanding of these issues is presented, with an emphasis on the relationship between the material properties of the gate stack, and the electrical properties of the devices. The combination of metal gates with high- κ gate dielectric appears to be a promising solution for the further scaling down of CMOS devices.

251 citations

Proceedings ArticleDOI
02 Dec 2001
TL;DR: In this article, the authors discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects for high-K dielectric integration into current Si technology.
Abstract: Reviews recent progress in and outlines the issues for high-K high-temperature (/spl sim/1000/spl deg/C) poly-Si CMOS processes and devices and also demonstrate possible solutions Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects Results on a variety of high-K candidates including HfO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2//Al/sub 2/O/sub 3/, ZrO/sub 2/, silicates, and AlN/sub y/(O/sub x/) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology

219 citations

Proceedings ArticleDOI
01 Jan 2016
TL;DR: In this paper, the authors report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices.
Abstract: We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies.

126 citations

Patent
Paul Zimmerman1, Matty Caymax1, Gendt Stefan De1, Annelies Delabie1, Lars-Ake Ragnarsson1 
10 Jul 2006
TL;DR: In this article, an ALD method for depositing a layer comprising the steps of providing a semiconductor substrate in a reactor, providing a pulse of a first precursor gas into the reactor, and providing an inert atmosphere in the reactor.
Abstract: The invention is related to an ALD method for depositing a layer comprising the steps of a) providing a semiconductor substrate in a reactor; b) providing a pulse of a first precursor gas into the reactor; c) providing a pulse of a second precursor gas into the reactor; d) providing an inert atmosphere in the reactor; and e) repeating step b) through step d), wherein at least once during step d) the semiconductor substrate is exposed to UV irradiation.

122 citations


Cited by
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Journal ArticleDOI
TL;DR: In this article, a review of the development of high-k gate oxides such as hafnium oxide (HFO) and high-K oxides is presented, with the focus on the work function control in metal gate electrodes.
Abstract: The scaling of complementary metal oxide semiconductor transistors has led to the silicon dioxide layer, used as a gate dielectric, being so thin (14?nm) that its leakage current is too large It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (?) or 'high K' gate oxides such as hafnium oxide and hafnium silicate These oxides had not been extensively studied like SiO2, and they were found to have inferior properties compared with SiO2, such as a tendency to crystallize and a high density of electronic defects Intensive research was needed to develop these oxides as high quality electronic materials This review covers both scientific and technological issues?the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure and reactions, their electronic structure, bonding, band offsets, electronic defects, charge trapping and conduction mechanisms, mobility degradation and flat band voltage shifts The oxygen vacancy is the dominant electron trap It is turning out that the oxides must be implemented in conjunction with metal gate electrodes, the development of which is further behind Issues about work function control in metal gate electrodes are discussed

1,520 citations

Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

Journal ArticleDOI
TL;DR: In this article, the choice of oxides, their structural and metallurgical behaviour, atomic diffusion, their deposition, interface structure and reactions, their electronic structure, bonding, band offsets, mobility degradation, flat band voltage shifts and electronic defects are discussed.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin (1.4 nm) that its leakage current is too large. It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (κ) or 'high K' gate oxides such as hafnium oxide and hafnium silicate. Little was known about such oxides, and it was soon found that in many respects they have inferior electronic properties to SiO2 ,s uch as a tendency to crystallise and a high concentration of electronic defects. Intensive research is underway to develop these oxides into new high quality electronic materials. This review covers the choice of oxides, their structural and metallurgical behaviour, atomic diffusion, their deposition, interface structure and reactions, their electronic structure, bonding, band offsets, mobility degradation, flat band voltage shifts and electronic defects. The use of high K oxides in capacitors of dynamic random access memories is also covered.

1,500 citations

Journal ArticleDOI
TL;DR: Puurunen et al. as discussed by the authors summarized the two-reactant ALD processes to grow inorganic materials developed to-date, updating the information of an earlier review on ALD.
Abstract: Atomic layer deposition (ALD) is gaining attention as a thin film deposition method, uniquely suitable for depositing uniform and conformal films on complex three-dimensional topographies. The deposition of a film of a given material by ALD relies on the successive, separated, and self-terminating gas–solid reactions of typically two gaseous reactants. Hundreds of ALD chemistries have been found for depositing a variety of materials during the past decades, mostly for inorganic materials but lately also for organic and inorganic–organic hybrid compounds. One factor that often dictates the properties of ALD films in actual applications is the crystallinity of the grown film: Is the material amorphous or, if it is crystalline, which phase(s) is (are) present. In this thematic review, we first describe the basics of ALD, summarize the two-reactant ALD processes to grow inorganic materials developed to-date, updating the information of an earlier review on ALD [R. L. Puurunen, J. Appl. Phys. 97, 121301 (2005)], and give an overview of the status of processing ternary compounds by ALD. We then proceed to analyze the published experimental data for information on the crystallinity and phase of inorganic materials deposited by ALD from different reactants at different temperatures. The data are collected for films in their as-deposited state and tabulated for easy reference. Case studies are presented to illustrate the effect of different process parameters on crystallinity for representative materials: aluminium oxide, zirconium oxide, zinc oxide, titanium nitride, zinc zulfide, and ruthenium. Finally, we discuss the general trends in the development of film crystallinity as function of ALD process parameters. The authors hope that this review will help newcomers to ALD to familiarize themselves with the complex world of crystalline ALD films and, at the same time, serve for the expert as a handbook-type reference source on ALD processes and film crystallinity.

1,160 citations