Solar Engineering Of Thermal Processes

Filtering and smoothing methods are used to produce an accurate estimate of the state of a time-varying system based on multiple observational inputs (data). Interest in these methods has exploded in recent years, with numerous applications emerging in fields such as navigation, aerospace engineering, telecommunications, and medicine. This compact, informal introduction for graduate students and advanced undergraduates presents the current state-of-the-art filtering and smoothing methods in a unified Bayesian framework. Readers learn what non-linear Kalman filters and particle filters are, how they are related, and their relative advantages and disadvantages. They also discover how state-of-the-art Bayesian parameter estimation methods can be combined with state-of-the-art filtering and smoothing algorithms. The book’s practical and algorithmic approach assumes only modest mathematical prerequisites. Examples include MATLAB computations, and the numerous end-of-chapter exercises include computational assignments. MATLAB/GNU Octave source code is available for download at www.cambridge.org/sarkka, promoting hands-on work with the methods.

贝叶斯滤波与平滑 (Bayesian filtering and smoothing)

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

This paper provides evidence that, as a result of constant-field scaling, the peak f T (approx. 0.3 mA/μm), peak f MAX (approx. 0.2 mA/μm), and optimum noise figure NF MIN (approx. 0.15 mA/pm) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers.

The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks

In recent years, inexact computing has been increasingly regarded as one of the most promising approaches for reducing energy consumption in many applications that can tolerate a degree of inaccuracy. Driven by the principle of trading tolerable amounts of application accuracy in return for significant resource savings - the energy consumed, the (critical path) delay and the (silicon) area being the resources - this approach has been limited to certain application domains. In this paper, we propose to expand the application scope, error tolerance as well as the energy savings of inexact computing systems through neural network architectures. Such neural networks are fast emerging as popular candidate accelerators for future heterogeneous multi-core platforms, and have flexible error tolerance limits owing to their ability to be trained. Our results based on simulated 65nm technology designs demonstrate that the proposed inexact neural network accelerator could achieve 43.91%-62.49% savings in energy consumption (with corresponding delay and area savings being 18.79% and 31.44% respectively) when compared to existing baseline neural network implementation, at the cost of an accuracy loss (quantified as the Mean Square Error (MSE) which increases from 0.14 to 0.20 on average).

Leveraging the error resilience of machine-learning applications for designing highly energy efficient accelerators

A simple algorithm (SAL) and a modified SAL (MSAL) for the estimation of the phase difference between two sine-wave signals are proposed. The results obtained by SAL and MSAL in simulations and on real samples are given. A comparison between the phase difference results estimated by MSAL, quadrature delay estimator (QDE), unbiased QDE (UQDE), three-parameter sine-fitting algorithm (3PSF), four-parameter sine-fitting algorithm (4PSF), and seven-parameter sine-fitting algorithm (7PSF) is presented. The requirements for the application of SAL and MSAL are analyzed.

A Simple Algorithm for the Estimation of Phase Difference Between Two Sinusoidal Voltages

Historically, hardware acceleration technologies have either been application-specific, therefore lacking in flexibility, or fully programmable, thereby suffering from notable inefficiencies on an application-by-application basis. To address the growing need for domain-specific acceleration technologies, this paper describes a design methodology (i) to automatically generate a domain-specific coarse-grained array from a set of representative applications and (ii) to introduce limited forms of architectural generality to increase the likelihood that additional applications can be successfully mapped onto it. In particular, coarse-grained arrays generated using our approach are intended to be integrated into customizable processors that use application-specific instruction set extensions to accelerate performance and reduce energy; rather than implementing these extensions using application-specific integrated circuit (ASIC) logic, which lacks flexibility, they can be synthesized onto our reconfigurable array instead, allowing the processor to be used for a variety of applications in related domains. Results show that our array is around $2\times$ slower and $15\times$ larger than an ultimately efficient ASIC implementation, and thus far more efficient than field-programmable gate arrays (FPGAs), which are known to be 3–4 $\times$ slower and 20–40 $\times$ larger. Additionally, we estimate that our array is usually around $2\times$ larger and $2\times$ slower than an accelerator synthesized using traditional datapath merging, which has, if any, very limited flexibility beyond the design set of DFGs.

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays

The control of movement in humans is hierarchical and distributed and uses feedback. An assistive system could be best integrated into the therapy of a human with a central nervous system lesion if the system is controlled in a similar manner. Here, we present a novel wireless architecture and routing protocol for a distributed functional electrical stimulation system that enables control of movement. The new system comprises a set of miniature battery-powered devices with stimulating and sensing functionality mounted on the body of the subject. The devices communicate wirelessly with one coordinator device, which is connected to a host computer. The control algorithm runs on the computer in open- or closed-loop form. A prototype of the system was designed using commercial, off-the-shelf components. The propagation characteristics of electromagnetic waves and the distributed nature of the system were considered during the development of a two-hop routing protocol, which was implemented in the prototype’s software. The outcomes of this research include a novel system architecture and routing protocol and a functional prototype based on commercial, off-the-shelf components. A proof-of-concept study was performed on a hemiplegic subject with paresis of the right arm. The subject was tasked with generating a fully functional palmar grasp (closing of the fingers). One node was used to provide this movement, while a second node controlled the activation of extensor muscles to eliminate undesired wrist flexion. The system was tested with the open- and closed-loop control algorithms. The system fulfilled technical and application requirements. The novel communication protocol enabled reliable real-time use of the system in both closed- and open-loop forms. The testing on a patient showed that the multi-node system could operate effectively to generate functional movement.

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Wireless distributed functional electrical stimulation system

Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%–109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.

Lazar Saranovac

Papers

A Simple Algorithm for the Estimation of Phase Difference Between Two Sinusoidal Voltages

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays

Wireless distributed functional electrical stimulation system

Flexible High Throughput QC-LDPC Decoder With Perfect Pipeline Conflicts Resolution and Efficient Hardware Utilization

Algorithm for EMG noise level approximation in ECG signals