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Lech Jozwiak

Researcher at Eindhoven University of Technology

Publications -  131
Citations -  1382

Lech Jozwiak is an academic researcher from Eindhoven University of Technology. The author has contributed to research in topics: Logic synthesis & Functional decomposition. The author has an hindex of 18, co-authored 130 publications receiving 1361 citations. Previous affiliations of Lech Jozwiak include Centre national de la recherche scientifique.

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A General Decomposition for Reversible Logic

TL;DR: This work presents for the first time a method that minimizes concurrently the number of gates, their total delay and the total garbage in reversible logic.
Proceedings ArticleDOI

Decomposition of multiple-valued functions

TL;DR: It is shown that the decomposition technique leads to additional compressing capabilities in PLA implementations, and another very promising area of application of decomposition is its effective representation of data in information systems, data bases and in other applications of information storing systems.

Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits

TL;DR: The synthesis method to RPGAs allows to realize arbitrary symmetric function in a completely regular structure of reversible gates with smaller “garbage” than the previously presented papers.
Proceedings ArticleDOI

Information relationships and measures: an analysis apparatus for efficient information system synthesis

TL;DR: The fundamental apparatus for the analysis and evaluation of information relationships is introduced and explained, which forms a complete information modeling and analysis apparatus that can be applied in logic design, decision system design, pattern recognition, knowledge discovery, machine learning and other areas.
Proceedings ArticleDOI

Non-disjoint decomposition of Boolean functions and its application in FPGA-oriented technology mapping

TL;DR: The non-disjoint serial decomposition and parallel decomposition is applied for efficient synthesis of FPGA-based circuits directed towards area or delay optimisation.