Lee Robert Levine

Bio: Lee Robert Levine is an academic researcher from Wilmington University. The author has contributed to research in topics: Wire bonding & Amplifier. The author has an hindex of 4, co-authored 7 publications receiving 105 citations.

Method of making low profile fine wire interconnections

Abstract: A novel method of making very low profile fine wire interconnections is accomplished with a conventional automatic gold wire ball bonder and includes the steps of making a conventional first ball bond and moving the bonding tool so as to pay out a length of wire that is shorter than the final desired length of wire to be used in the interconnection. The bonding tool is movingly engaged against the target on which the second bond is to be made employing a first bonding force which bends and conforms the wire beneath the working face of the capillary bonding tool and simultaneously forward extrudes and wire draws the neck of the fine wire into a tapered section which avoids backward extrusion. Subsequently a second bond force and ultrasonic energy is applied at the second bond target position to generate a conventional thermosonic second bond. The fine wire is bonded to the target by a thermocompression bond resulting from the moving first bonding force and the bond is interconnected to a conventional thermosonic bond resulting from the second bond force which produces a larger and stronger bond area than a conventional prior art second bond.

Method of making constant clearance flat link fine wire interconnections

Abstract: A method of pre-forming a length of fine wire while simultaneously making a fire wire interconnection between a first and a second bonding point on a semiconductor device includes the steps of teaching the location of the edges of the die and teaching a plane in space which is located away from the edges of said die. After teaching the height of the clearance above the die and the XYZ location of the first and second bonding points the automatic wire bonder in directed to generate a desired geometric link profile between bonding points which defines the length of links L1, L2 and L3. Using the geometric profile and empirically determined constants the automatic wire bonder calculates a tool trajectory for pre-forming the fine wire while simultaneously making a fine wire interconnection with an automatic wire bonder.

High yield clampless wire bonding method

Abstract: The present invention method is carried out with a programmable automatic wire bonder having a linear drive motor. The wire bonder is programmed to bond loose lead frame leads at a second bond position in a novel manner. The lead frame lead to be bonded at second bond is clamped in a work holder that leaves the ends of the lead frame leads loose above the bonding mandrel of the work holder but restrained to a predetermined floating zone that is established within a predetermined distance above the bonding mandrel. The bondig tool is programmed to engage the loose lead frame lead at second bond at a predetermined velocity which permits the bonding tool to simultaneously exert an impact force on the wire to be bonded and to clamp the loose lead frame lead. While the bonding tool is applying the impact force and simultaneously clamping the loose lead frame lead a second relatively high bonding force is applied to the bonding tool to complete a second bond without incurring bounce, or transient vibrations while making the second bond.

Multi-frequency ultrasonic wire bonder and method

Abstract: The present invention includes a multi-frequency ultrasonic generator coupled to a multi-resonance frequency transducer capable of operating at a plurality of usable resonance frequencies A controller is coupled to a power amplifier that drives the ultrasonic transducer and is capable of applying power, voltage or current profiles for each of the resonance frequencies to be used during a bonding operation independent of the others

Multichip module having a stacked chip arrangement

Abstract: A multichip module includes: a) a multichip module substrate; b) a first chip, the first chip having opposed base and bonding faces, the base face being adhered to the multichip module substrate, the first chip bonding face including a central area and a plurality of bonding pads peripheral to the central area; c) a second chip, the second chip having opposed base and bonding faces, the second chip bonding face including a central area and a plurality of peripheral bonding pads; d) a first/second adhesive layer interposed between and connecting the first chip bonding face and the second chip base face, the first/second adhesive layer having a thickness and a perimeter, the perimeter being positioned within the central area inside of the peripheral bonding pads; e) a plurality of first loop bonding wires bonded to and between the respective first chip bonding pads and the multichip module substrate, the respective first bonding wires having outwardly projecting loops of a defined loop height, the thickness of the adhesive layer being greater than the loop height to displace the second chip base face in a non-contacting relationship above and with respect to the first wires; and f) a plurality of second loop bonding wires bonded to and between the respective second chip bonding pads and the multichip module substrate.

Chip size semiconductor packages with stacked dies

Abstract: Chip-size semiconductor packages (“CSPs”) containing multiple stacked dies are disclosed The dies are mounted on one another in a stack such that corresponding ones of the vias in the respective dies are coaxially aligned An electrically conductive wire or pin is in each set of aligned vias and soldered to corresponding ones of the terminal pads The pins include portions protruding from the stack of dies that serve as input-output terminals of the package Heat spreaders can be interleaved between the stacked dies to enhance heat dissipation from the package

Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding

Abstract: A ball grid array semiconductor device (10) includes a package substrate (14 or 16) having a plurality of conductive traces (18), bond posts (20), and conductive vias (22). A semiconductor die (12) is mounted to the package substrate. Orthogonal wire bonds (28) are used to electrically connect staggered bond pads (26) to corresponding bond posts (20) on the substrate. A liquid encapsulant (40) is used to cover the die, the wire bonds, and portions of the package substrate. In another embodiment, a package substrate (50) includes a lower bonding tier (52) and an upper bonding tier (54). Wire bonds (60) are used to electrically connect an outer row of bond pads (64) to bond posts (20) of lower tier (52), while wire bonds (62) are used to electrically connect an inner row of bond pads (64) to bond posts (20) of an upper tier (54). The loop height of wire bonds (60) is smaller than that of wire bonds (62).

Making semiconductor packages with stacked dies and reinforced wire bonds

Abstract: This invention provides a method for making a semiconductor package with stacked dies that substantially reduces risk of fracturing of the dies and prevents breakage of the wire bonds caused by wire sweep. One embodiment of the method includes the provision of a substrate and a pair of semiconductor dies, each having opposite top and bottom surfaces and a plurality of wire bonding pads around the peripheries of their respective top surfaces. One die is attached and wire bonded to a top surface of the substrate. A measured quantity of an uncured, fluid adhesive is dispensed onto the top surface of the first die, and the adhesive is squeezed out to the edges of the dies by pressing the bottom surface of the second die down onto the adhesive until the two dies are separated by a layer of the adhesive. The adhesive is cured and the second die is wire bonded to the substrate. A bead of an adhesive is dispensed around the periphery of the dies such that it covers the wire bonds and bonding pads on the second die. A plastic body is molded over the dies and the bead of adhesive. The bead of adhesive prevents bending or breakage of the wire bonds caused by wire sweep during the subsequent molding operation.

Semiconductor device and manufacturing method thereof

Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.