The ever increasing requirements for electrical performance of on-chip wiring has driven three major technological advances in recent years. First, copper has replaced Aluminum as the new interconnect metal of choice, forcing also the introduction of damascene processing. Second, alternatives for SiO2 with a lower dielectric constant are being developed and introduced in main stream processing. The many new resulting materials needs to be classified in terms of their materials characteristics, evaluated in terms of their properties, and tested for process compatibility. Third, in an attempt to lower the dielectric constant even more, porosity is being introduced into these new materials. The study of processes such as plasma interactions and swelling in liquid media now becomes critical. Furthermore, pore sealing and the deposition of a thin continuous copper diffusion barrier on a porous dielectric are of prime importance. This review is an attempt to give an overview of the classification, the character...

Low dielectric constant materials for microelectronics

In this paper we present a novel and versatile t e c h n i q u e f o r t h e p r o d u c t i o n o f u l t r a f i n e m e t a l p a r t i c l e s by evaporation from a temperature‐regulated oven containing a reduced atmosphere of an inert gas. An extensive investigation of particles of oxidized Al, with diameters of 3 to 6 nm, has been performed. We have also studied ultrafine particles of Mg,Zn, and Sn produced in the same manner. A supplementing investigation has been carried out for particles of Cr, Fe, Co, Ni, Cu, and Ga, as well as larger Al particles, produced by ’’conventional’’ inert‐gas evaporation from a resistive filament. Diameter as a function of evaporation rate, inert‐gas pressure, and the kind of inert gas are reported. Crystalline particles smaller than 20 nm look almost spherical in the electron microscope, while larger ones often display pronounced crystal habit. S i z e d i s t r i b u t i o n s have been investigated in detail, and consistently the logarithm of the particle diameter has a Gaussian distribution to a high precision for the smallest sizes, whereas larger particles deviate from such a simple behavior. A statistical growth model, based on the Central Limit Theorem, has been formulated for liquidlike coalescence of particles; this theory accounts satisfactorily for all our data, as well as for most size distributions published in the literature. Applications of the model to colloids, discontinuous films, and supported catalysts are discussed. By comparing size distributions for particles produced by a variety of techniques we found a number of empirical rules for the width of the distributions, as defined by a (geometric) standard deviation σ. For crystalline inert‐gas‐ evaporated particles we obtained consistently 1.36?σ?1.60; for coalescing islands in discontinuous films we found 1.22?σ?1.34; and similar rules are applicable to colloids, supported catalysts, and to ultrafine droplets.

Ultrafine metal particles

Transparent conductors as solar energy materials: A panoramic review

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

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3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

This review presents an overview of the thermal properties of mesoscopic structures. The discussion is based on the concept of electron energy distribution, and, in particular, on controlling and probing it. The temperature of an electron gas is determined by this distribution: refrigeration is equivalent to narrowing it, and thermometry is probing its convolution with a function characterizing the measuring device. Temperature exists, strictly speaking, only in quasiequilibrium in which the distribution follows the Fermi-Dirac form. Interesting nonequilibrium deviations can occur due to slow relaxation rates of the electrons, e.g., among themselves or with lattice phonons. Observation and applications of nonequilibrium phenomena are also discussed. The focus in this paper is at low temperatures, primarily below $4\phantom{\rule{0.3em}{0ex}}\mathrm{K}$, where physical phenomena on mesoscopic scales and hybrid combinations of various types of materials, e.g., superconductors, normal metals, insulators, and doped semiconductors, open up a rich variety of device concepts. This review starts with an introduction to theoretical concepts and experimental results on thermal properties of mesoscopic structures. Then thermometry and refrigeration are examined with an emphasis on experiments. An immediate application of solid-state refrigeration and thermometry is in ultrasensitive radiation detection, which is discussed in depth. This review concludes with a summary of pertinent fabrication methods of presented devices.

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Opportunities for mesoscopics in thermometry and refrigeration: Physics and applications

Handbook of Thin Film Technology

The operation of rf discharges is described and the internal distribution of voltages is considered. The significance of this with respect to sputtering, particularly of insulators, is then discussed. An equivalent circuit for the discharge is presented and the influence of such parameters as pressure and magnetic field on the components of this circuit is described. Finally, energy distributions for positive ions, electrons, and negative ions incident at the substrate during deposition are given.

Application of RF discharges to sputtering

After a discussion of the reasons for choosing to implement logic in array form. a detailed description of the nature of array logic is given. Topics specifically discussed include general array structures and implementation, influence of decoder partitioning, design of logic arrays, output phase, "split" variables, feedback in logic arrays, and reconfiguration.

An introduction to array logic

Handbook of thin film technology

An improved technique for measuring re-emission coefficients is described and data on the effect of temperature are presented. These are discussed in the light of a physical model of film growth during sputtering where in constant re-emission of material throughout deposition occurs. Evidence is then presented that such re-emission is essential if films of high quality are to be obtained. To help assess "quality" in a quantitative fashion use has been made of the PBUT (pin-hole breakup thickness) phenomenon, whichis described in some detail. The influence on PBUT of several system parameters such as sputtering pressure and impurity content is discussed and related to the re-emission coefficient.

Leon I Maissel

Papers

Handbook of Thin Film Technology

Application of RF discharges to sputtering

An introduction to array logic

Handbook of thin film technology

Re-emission of sputtered SiO 2 , during growth and its relation to film quality