Leonard R. Rockett

Bio: Leonard R. Rockett is an academic researcher from BAE Systems. The author has contributed to research in topics: CMOS & Integrated circuit. The author has an hindex of 10, co-authored 16 publications receiving 211 citations.

Radiation Hardened FPGA Technology for Space Applications

Abstract: High performance, high density, radiation hardened Field Programmable Gate Arrays (FPGAs) are in great demand for military and space applications to reduce design cost and cycle time. BAE Systems has implemented radiation hardened 150nm bulk CMOS process technology in its foundry located in Manassas, VA to support such advanced product needs. BAE Systems and Actel Corporation are collaborating to bring the next-generation radiation hardened FPGA product for space applications to market. This paper will describe the rad hard AX-250 FPGA and the electrical and radiation test data on rad hard 150nm product hardware, FPGA device structures and anti-fuse arrays, as part of the overall FPGA product installation and qualification effort.

Proton and gamma radiation effects in a new first-generation SiGe HBT technology

Abstract: The effects of proton and gamma irradiation on a new commercially available SiGe technology are investigated for the first time. The results of proton irradiation on a differential SiGe HBT LC oscillator are also reported in order to gauge circuit-level impact. These findings indicate that the dc, ac, and RF circuit performance is total dose tolerant up to Mrad-level equivalent total dose. A technology comparison is drawn between the results of this work and the three other previously reported SiGe technologies. We find that all reported SiGe HBT technologies to date show acceptable proton radiation tolerance up to Mrad levels. Transistor mismatch is also investigated here for the first time in SiGe HBTs. Collector current mismatch data as a function of emitter geometry are reported both before and after exposure for this SiGe HBT technology. We find only minimal changes in device-to-device mismatch after radiation exposure, suggesting that these SiGe HBTs should be suitable for use in analog circuits, which are critically dependent on the matching characteristics of the requisite devices.

Single-event upset hardened reconfigurable bi-stable CMOS latch

Abstract: The present invention provides a single-event upset (SEU) hardened integrated circuit. The integrated circuit includes an SEU hardened asymmetric bi-stable CMOS latch having a first logic state and a second logic state. A supply voltage is operably coupled to the asymmetric bi-stable latch, where upon activation of the supply voltage the asymmetric bi-stable latch is always set to the first logic state. A switch may be provided for changing the latch from the first logic state to the second logic state.

High-performance high-density cmos sram cell

Abstract: A high-performance high-density CMOS SRAM cell (MC) having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors (TA/TC; TB/TD) serially connected between V dd and circuit ground to form a first inverter with a first data node ( 1 ) between the two transistors (TA/TC) of the first inverter, and, in a similar manner, to form a second inverter with a second data node ( 2 ) between the two transistors (TB/TD) of the second inverter. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. An access transistor (TE) is connected between a bit line (BL) and the first data node ( 1 ) to provide data access thereto. A diode (D) is connected between the data node of one of the inverters and the common gate connection of the other inverter to facilitate the “write one” operation. The diode (D) can be implemented in dual work function polysilicon topologies by selectively doping adjacent regions of the single gate level polysilicon with an appropriate polysilicon doping type and concentration for each transistor type to form a PN junction ( 16 ) in the polysilicon ( 18 ). A window or opening ( 20 ) is formed in the silicide strapping layer ( 18 ) to enable the PN junction ( 16 ) operation.

A radiation hardened reconfigurable FPGA

Abstract: A new high density, high performance radiation hardened, reconfigurable Field Programmable Gate Array (FPGA) is being developed by Achronix Semiconductor and BAE Systems for use in space and other radiation hardened applications. The reconfigurable FPGA fabric architecture utilizes Achronix Semiconductor novel picoPIPE technology and it is being manufactured at BAE Systems using their strategically radiation hardened 150 nm epitaxial bulk CMOS technology, called RH15. Circuits built in RH15 consistently demonstrate megarad total dose hardness and the picoPIPE asynchronous technology has been adapted for use in space with a Redundancy Voting Circuit (RVC) methodology to protect the user circuits from single event effects.

Dynamically replicated memory: building reliable systems from nanoscale resistive memories

Abstract: DRAM is facing severe scalability challenges in sub-45nm tech- nology nodes due to precise charge placement and sensing hur- dles in deep-submicron geometries. Resistive memories, such as phase-change memory (PCM), already scale well beyond DRAM and are a promising DRAM replacement. Unfortunately, PCM is write-limited, and current approaches to managing writes must de- commission pages of PCM when the first bit fails. This paper presents dynamically replicated memory (DRM), the first hardware and operating system interface designed for PCM that allows continued operation through graceful degradation when hard faults occur. DRM reuses memory pages that con- tain hard faults by dynamically forming pairs of complementary pages that act as a single page of storage. No changes are required to the processor cores, the cache hierarchy, or the operating sys- tem's page tables. By changing the memory controller, the TLBs, and the operating system to be DRM-aware, we can improve the lifetime of PCM by up to 40x over conventional error-detection techniques.

Present and Future Non-Volatile Memories for Space

Abstract: We discuss non-volatile memories (NVM) for space applications. The focus will be both on technologies and devices aimed at the mainstream commercial markets and on rad-hard devices. Commercial NVMs are very attractive for space designers due to their large size (tens of Gbits), even though they have several issues related to ionizing radiation. Rad-hard NVMs offer radiation hardness, but are available only in small size (few Mbits). Most of the emphasis in this review paper will be on the current dominant technology in the mainstream market: floating gate flash memories. A comprehensive discussion of total dose and single event effects results for a wide cross section of NVMs will be presented. Finally, we will conclude with a cursory glance at other emerging non-volatile technologies.

Electrical conduction in chalcogenide glasses of phase change memory

Abstract: Amorphous chalcogenides have been extensively studied over the last half century due to their application in rewritable optical data storage and in non-volatile phase change memory devices. Yet, the nature of the observed non-ohmic conduction in these glasses is still under debate. In this review, we consolidate and expand the current state of knowledge related to dc conduction in these materials. An overview of the pertinent experimental data is followed by a review of the physics of localized states that are peculiar to chalcogenide glasses. We then describe and evaluate twelve relevant transport mechanisms with conductivities that depend exponentially on the electric field. The discussed mechanisms include various forms of Poole-Frenkel ionization, Schottky emission, hopping conduction, field-induced delocalization of tail states, space-charge-limited current, field emission, percolation band conduction, and transport through crystalline inclusions. Most of the candidates provide more or less satisfactory fits of the observed non-linear IV data. Our analysis calls upon additional studies that would enable one to discriminate between the various alternative models.

Radiation Effects in SiGe Technology

Abstract: Silicon-Germanium (SiGe) technology effectively merges the desirable attributes of conventional silicon-based CMOS manufacturing (high integration levels, at high yield and low cost) with the extreme levels of transistor performance attainable in classical III-V heterojunction bipolar transistors (HBTs). SiGe technology joins together on-die high-speed bandgap-engineered SiGe HBTs with conventional Si CMOS to form SiGe BiCMOS technology, including all the requisite RF passive elements and multi-level thick-Al metalization required for high-speed circuit design. Such an silicon-based integrated circuit technology platform presents designers with an ideal division of labor for realizing optimal solutions to many performance-constrained mixed-signal (analog + digital + RF) systems. The unique bandgap-engineered features of SiGe HBTs enable several key merits with respect to operation across a wide variety of so-called “extreme environments”, potentially with little or no process modification, ultimately providing compelling advantages at the circuit and system level, across a wide class of envisioned commercial and defense applications. Here we give an overview of this interesting field, focusing primarily on the intersection of SiGe HBTs, and circuits built from them, with radiation-intense environments such as space.

Semiconductor memory device.

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.