Matrix Factorization Techniques for Recommender Systems

The increasing integration of the Internet of Everything into the industrial value chain has built the foundation for the next industrial revolution called Industrie 4.0. Although Industrie 4.0 is currently a top priority for many companies, research centers, and universities, a generally accepted understanding of the term does not exist. As a result, discussing the topic on an academic level is difficult, and so is implementing Industrie 4.0 scenarios. Based on a quantitative text analysis and a qualitative literature review, the paper identifies design principles of Industrie 4.0. Taking into account these principles, academics may be enabled to further investigate on the topic, while practitioners may find assistance in identifying appropriate scenarios. A case study illustrates how the identified design principles support practitioners in identifying Industrie 4.0 scenarios.

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Design Principles for Industrie 4.0 Scenarios

The cloud heralds a new era of computing where application services are provided through the Internet. Cloud computing can enhance the computing capability of mobile systems, but is it the ultimate solution for extending such systems' battery lifetimes?

Cloud Computing for Mobile Users: Can Offloading Computation Save Energy?

Power management is an important concern in sensor networks, because a tethered energy infrastructure is usually not available and an obvious concern is to use the available battery energy efficiently. However, in some of the sensor networking applications, an additional facility is available to ameliorate the energy problem: harvesting energy from the environment. Certain considerations in using an energy harvesting source are fundamentally different from that in using a battery, because, rather than a limit on the maximum energy, it has a limit on the maximum rate at which the energy can be used. Further, the harvested energy availability typically varies with time in a nondeterministic manner. While a deterministic metric, such as residual battery, suffices to characterize the energy availability in the case of batteries, a more sophisticated characterization may be required for a harvesting source. Another issue that becomes important in networked systems with multiple harvesting nodes is that different nodes may have different harvesting opportunity. In a distributed application, the same end-user performance may be achieved using different workload allocations, and resultant energy consumptions at multiple nodes. In this case, it is important to align the workload allocation with the energy availability at the harvesting nodes. We consider the above issues in power management for energy-harvesting sensor networks. We develop abstractions to characterize the complex time varying nature of such sources with analytically tractable models and use them to address key design issues. We also develop distributed methods to efficiently use harvested energy and test these both in simulation and experimentally on an energy-harvesting sensor network, prototyped for this work.

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Power management in energy harvesting sensor networks

Indoor localization has recently witnessed an increase in interest, due to the potential wide range of services it can provide by leveraging Internet of Things (IoT), and ubiquitous connectivity. Different techniques, wireless technologies and mechanisms have been proposed in the literature to provide indoor localization services in order to improve the services provided to the users. However, there is a lack of an up-to-date survey paper that incorporates some of the recently proposed accurate and reliable localization systems. In this paper, we aim to provide a detailed survey of different indoor localization techniques, such as angle of arrival (AoA), time of flight (ToF), return time of flight (RTOF), and received signal strength (RSS); based on technologies, such as WiFi, radio frequency identification device (RFID), ultra wideband (UWB), Bluetooth, and systems that have been proposed in the literature. This paper primarily discusses localization and positioning of human users and their devices. We highlight the strengths of the existing systems proposed in the literature. In contrast with the existing surveys, we also evaluate different systems from the perspective of energy efficiency, availability, cost, reception range, latency, scalability, and tracking accuracy. Rather than comparing the technologies or techniques, we compare the localization systems and summarize their working principle. We also discuss remaining challenges to accurate indoor localization.

A Survey of Indoor Localization Systems and Technologies

Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these networks get deployed in a wide range of new applications, where power is becoming a key design constraint, we need to seriously consider power efficiency in designing interconnection networks. As the demand for network bandwidth increases, communication links, already a significant consumer of power now, will take up an ever larger portion of total system power budget. In this paper we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. We propose a history-based DVS policy that judiciously adjusts link frequencies and voltages based on past utilization. Our approach realizes up to 6.3/spl times/ power savings (4.6/spl times/ on average). This is accompanied by a moderate impact on performance (15.2% increase in average latency before network saturation and 2.5% reduction in throughput.) To the best of our knowledge, this is the first study that targets dynamic power optimization of interconnection networks.

https://www.cs.ucr.edu/~gupta/hpca9/HPCA-PDFs/09-shang.pdf

Dynamic voltage scaling with links for power optimization of interconnection networks

High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

This paper analyzes the dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) by taking advantage of both simulation and measurement. Our target device is Xilinx Virtex™-II family, which contains the most recent and largest programmable fabric. We identify important resources in the FPGA architecture and obtain their utilization, using a large set of real designs. Then, using a number of representative case studies we calculate the switching activity corresponding to each resource. Finally, we combine effective capacitance of each resource with its utilization and switching activity to estimate its share of power consumption. According to our results, the power dissipation share of routing, logic and clocking resources are 60%, 16%, and 14%, respectively. Also, we concluded that dynamic power dissipation of a Virtex-II CLB is 5.9mW per MHz for typical designs, but it may vary significantly depending on the switching activity.

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Dynamic power consumption in Virtex™-II FPGA family

 Advances in embedded systems and low-cost gas sensors are enabling a new wave of low-cost air quality monitoring tools Our team has been engaged in the development of low-cost, wearable, air quality monitors (M-Pods) using the Arduino platform These M-Pods house two types of sensors – commercially available metal oxide semiconductor (MOx) sensors used to measure CO, O3, NO2, and total VOCs, and NDIR sensors used to measure CO2 The MOx sensors are low in cost and show high sensitivity near ambient levels; however they display non-linear output signals and have cross-sensitivity effects Thus, a quantification system was developed to convert the MOx sensor signals into concentrations We conducted two types of validation studies – first, deployments at a regulatory monitoring station in Denver, Colorado, and second, a user study In the two deployments (at the regulatory monitoring station), M-Pod concentrations were determined using collocation calibrations and laboratory calibration techniques M-Pods were placed near regulatory monitors to derive calibration function coefficients using the regulatory monitors as the standard The form of the calibration function was derived based on laboratory experiments We discuss various techniques used to estimate measurement uncertainties The deployments revealed that collocation calibrations provide more accurate concentration estimates than laboratory calibrations During collocation calibrations, median standard errors ranged between 40–61 ppb for O3, 64–84 ppb for NO2, 028–044 ppm for CO, and 168 ppm for CO2 Median signal to noise (S / N) ratios for the M-Pod sensors were higher than the regulatory instruments: for NO2, 36 compared to 234; for O3, 14 compared to 16; for CO, 11 compared to 100; and for CO2, 422 compared to 300–500 By contrast, lab calibrations added bias and made it difficult to cover the necessary range of environmental conditions to obtain a good calibration A separate user study was also conducted to assess uncertainty estimates and sensor variability In this study, 9 M-Pods were calibrated via collocation multiple times over 4 weeks, and sensor drift was analyzed, with the result being a calibration function that included baseline drift Three pairs of M-Pods were deployed, while users individually carried the other three The user study suggested that inter-M-Pod variability between paired units was on the same order as calibration uncertainty; however, it is difficult to make conclusions about the actual personal exposure levels due to the level of user engagement The user study provided real-world sensor drift data, showing limited CO drift (under −005 ppm day−1), and higher for O3 (−26 to 20 ppb day−1), NO2 (−156 to 051 ppb day−1), and CO2 (−42 to 31 ppm day−1) Overall, the user study confirmed the utility of the M-Pod as a low-cost tool to assess personal exposure

/pdf/the-next-generation-of-low-cost-personal-air-quality-sensors-ai0frs5hjv.pdf

The next generation of low-cost personal air quality sensors for quantitative exposure monitoring

It has been the conventional assumption that, due to the superlinear dependence of leakage power consumption on temperature, and widely varying on-chip temperature profiles, accurate leakage estimation requires detailed knowledge of thermal profile. Leakage power depends on integrated circuit (IC) thermal profile and circuit design style. The authors show that linear models can be used to permit highly-accurate leakage estimation over the operating temperature ranges in real ICs. The authors then show that for typical IC packages and cooling structures, a given amount of heat introduced at any position in the active layer will have similar impact on the average temperature of the layer. These two observations allow us to prove that, for wide ranges of design styles and operating temperatures, extremely fast, coarse-grained thermal models, combined with linear leakage power consumption models, permit highly-accurate system-wide leakage power consumption estimation. The results of our proofs are further confirmed via comparisons with leakage estimation based on detailed, time-consuming thermal analysis techniques. Experimental results indicate that the proposed technique yields a 59,259times-1,790,000times speedup in leakage power estimation while maintaining accuracy

/pdf/accurate-temperature-dependent-integrated-circuit-leakage-170i1fhk6r.pdf

Li Shang

Papers

Dynamic voltage scaling with links for power optimization of interconnection networks

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

Dynamic power consumption in Virtex™-II FPGA family

The next generation of low-cost personal air quality sensors for quantitative exposure monitoring

Accurate temperature-dependent integrated circuit leakage power estimation is easy