In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain-current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed

A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs

Effective pregate surface passivation and postgate treatments are very important to optimize the germanium metal-oxide-semiconductor (MOS) interface quality. In this work, pregate GeO2 surface passivation and postgate treatments including CF4-plasma treatment and forming gas annealing are employed to make high quality HfO2 gated germanium MOS capacitors. Excellent electrical characteristics with negligible capacitance-voltage stretch-out and frequency dispersion are achieved. The interface trap density of TaN∕HfO2∕GeOx∕Ge MOS structure is as low as 2.02×1011cm−2eV−1 at the minimum. Comparing to the forming gas annealing, it is found that CF4-plasma treatment is more effective to passivate interface states located in the upper half of Ge bandgap.

Effects of fluorine incorporation and forming gas annealing on high-k gated germanium metal-oxide-semiconductor with GeO2 surface passivation

개인정보 보호법 : private information

We review the origins, recent developments and present status of silicon-on-insulator (SOI) MOSFET technology which is becoming the technology of choice in mainstream CMOS circuits for VLSI as well as for other high frequency applications in the low-GHz range The different basic multi-gate three dimensional SOI structures that are especially amenable to high speed operation are analyzed, compared and discussed

Multi-gate 3-D SOI MOSFETs as the mainstream technology in high speed CMOS applications

Uniaxial stress enhanced hole mobility is measured for (100)/⟨110⟩ silicon (Si) p-channel metal-oxide-semiconductor field-effect transistor from 300 to 87 K. For the technologically important longitudinal compressive stress along ⟨110⟩, the percent change in the uniaxial stress enhanced hole mobility is observed to increase at lower temperatures, which is opposite to the trend for biaxially stressed devices. The stress enhanced mobility is compared with six band k⋅p with finite difference formalism, which shows that the larger mobility gain at lower temperatures results from greater uniaxial stress induced hole conductivity mass reduction. The larger mass reduction results from more holes occupying states at the band edge, which have a light hole conductivity mass in the channel direction. For the uniaxial stress range in this work (<500 MPa), negligible strain altered phonon and surface roughness scattering rates are observed.

Temperature dependence of enhanced hole mobility in uniaxial strained p-channel metal-oxide-semiconductor field-effect transistors and insight into the physical mechanisms

Effective mobility measurements have been made at 4.2 K on high performance high-k gated germanium p-type metal-oxide-semiconductor field effect transistors with a range of Ge/gate dielectric interface state densities. The mobility is successfully modelled by assuming surface roughness and interface charge scattering at the SiO2 interlayer/Ge interface. The deduced interface charge density is approximately equal to the values obtained from the threshold voltage and subthreshold slope measurements on each device. A hydrogen anneal reduces both the interface state density and the surface root mean square roughness by 20%.

/pdf/low-temperature-mobility-in-hafnium-oxide-gated-germanium-p-2agt3wix5b.pdf

Low temperature mobility in hafnium-oxide gated germanium p-channel metal-oxide-semiconductor field-effect transistors

A review of SOI transistor models

FinFET devices are extensively investigated due to the prospects for application in the sub-100nm CMOS integrated circuits fabrication. Small size of the FinFETs and the properties of technological processes strongly influence their electrical characteristics. The random variations of the characteristics lead to a mismatch effect critical from the viewpoint of design and fabrication. In the paper different types of the variations of FinFET characteristics are discussed. The considerations are illustrated with measurement data of a series of devices and with distributions of the parameters extracted from these data. Possible effect of the parameter variability on digital cell parameters is analyzed.

Fluctuations of electrical characteristics of FinFET devices

Investigation of radicals kinetic behavior and estimation of radical sticking coefficient become indispensable for establishing plasma processing control by its internal parameters. This approach is required for plasma processing of single-nanometer gate length field effect transistors and 3-diemnsional gates in particular. In our works we have developed new technique for radicals kinetic behavior investigation and its sticking coefficient estimation. Our approach is based on application of parallel plate structure in conjunction with numerical analysis. This approach allows for radicals behavior investigation apart from ions and ultraviolet photons. Moreover this approach allows for analysis role of radical direct and indirect fluxes. By comparison of measured profile thickness and simulated stuck radicals profile we were able to estimate hydrogen radical sticking probability to ArF photoresist.

/pdf/sticking-coefficient-of-hydrogen-radicals-on-arf-photoresist-2a784cvkxo.pdf

Sticking coefficient of hydrogen radicals on ArF photoresist estimated by parallel plate structure in conjunction with numerical analysis

A new non-quasi static small-signal model of partially-depleted SOI MOSFETs is presented together with parameter extraction procedure. A method to eliminate parasitic capacitances from experimental data is also shown.

https://ieeexplore.ieee.org/iel5/7865/21660/01004035.pdf

Lidia Lukasiak

Papers

Low temperature mobility in hafnium-oxide gated germanium p-channel metal-oxide-semiconductor field-effect transistors

A review of SOI transistor models

Fluctuations of electrical characteristics of FinFET devices

Sticking coefficient of hydrogen radicals on ArF photoresist estimated by parallel plate structure in conjunction with numerical analysis

Small-signal model of partially-depleted SOI MOSFETs and its parameter extraction