In this article, commercially 1200-V asymmetric and double trench silicon carbide (SiC) metal–oxide–semiconductor-field-effect transistors ( mosfet s) from two manufacturers are investigated by experiment and finite-element simulation under single-pulse unclamped inductive switching (UIS) stress. The variation in avalanche time with mosfet avalanche energy and temperatures dependence of critical avalanche energy and maximum power dissipation are evaluated. It is found that two failure mechanisms are identified, i.e., thermal runaway and gate oxide rupture. For asymmetric trench SiC mosfet s, the failure mode are all thermal runaway at various temperatures. However, the failure mode of double trench SiC mosfet s is thermal runaway or gate oxide rupture, which indicates an instable avalanche robustness under UIS stress. The variations of dc parameters are recorded to evaluate external features of device failure. Furthermore, finite-element simulation is used to reveal the electro-thermal stress inside the device during avalanche. Finally, failed devices are decapsulated to verify the location of failure point from the perspective of the semiconductor die.

Investigation and Failure Mode of Asymmetric and Double Trench SiC mosfet s Under Avalanche Conditions

In this article, short-circuit capability prediction and failure mode of 1200-V-class SiC MOSFET s with a double and asymmetric trench structure are proposed under single-pulse short-circuit stress. A short-circuit prediction model is established to evaluate short-circuit withstand time and corresponding critical energy of devices under various dc bus voltages. This model can provide quick predictive guidance even if there are few test results, and the predicted values are consistent with practical values. Furthermore, two failure modes are investigated in a short-circuit test. For asymmetric trench SiC MOSFET s, failure modes are gate damage at lower dc bus voltages and thermal runaway at higher dc bus voltages; whereas failure mode for double trench SiC MOSFET s is thermal runaway at all dc bus voltages. In addition, the internal thermal-electro stress of the device is analyzed until it fails during short-circuit condition, and proves that failure mode depends on the dc bus voltage and peak short-circuit current of the device. Finally, the top view of failed devices confirms the two failure modes of trench SiC MOSFET s by the postdecapsulation.

Short-Circuit Capability Prediction and Failure Mode of Asymmetric and Double Trench SiC MOSFETs

In this article, the performance and triggering mechanism of the single-event burnout (SEB) of a 4H-SiC trench-gate (TG) MOSFET structure are evaluated by the 2-D numerical simulations. The novel N+ island buffer 4H-SiC TG MOSFET and the conventional TG 4H-SiC MOSFET are analyzed and compared to examine whether an N+ island region introduced in the second buffer can effectively reduce the impact ionization located at the N− drift/N+ buffer junction and improve device tolerance to the SEB. The TCAD simulation results revealed that compared with the conventional structure, which is a simple double-buffer structure, the N+ island buffer-hardened structure changed the burnout threshold voltage, improving the SEB performance significantly. In addition, the results proved that the impact ionization played an important role in the SEB triggering mechanism, significantly affecting the SEB performance of the 4H-SiC TG MOSFET. The performance of the hardened N+ island buffer with a different dopant concentration of N-buffer 2 and a size of N+ island is discussed. The specific burnout threshold voltage at the optimal parameters of the proposed structure is 47% higher than that of the conventional structure.

Single-Event Burnout Hardness for the 4H-SiC Trench-Gate MOSFETs Based on the Multi-Island Buffer Layer

Major recent developments in growth expertise related to the cubic polytype of Silicon Carbide, the 3C-SiC, coupled with its remarkable physical properties and the low fabrication cost, suggest that within the next years, 3C-SiC devices can become a commercial reality. Inevitably, a comparison to the most well-developed polytype of SiC, the 4H-SiC, should exist. It is, therefore, important to develop finite element method techniques and models for accurate device design, analysis, and comparison. It is also needed to perform an exhaustive investigation with scope to identify which family of devices, which voltage class, and for which applications this polytype is best suited. In this paper, we validate the recently developed technology computer-aided design (TCAD) material models for 3C-SiC and those of 4H-SiC with measurements on power diodes. An excellent agreement between measurements and TCAD simulations was obtained. Thereafter, based on this validation, 3C- and 4H-SiC vertical power diodes are assessed to create trade-off maps. Depending on the operation requirements imposed by the application, the developed tradeoff maps set the boundary of the realm for those two polytypes and allows to predict which applications would benefit once electrically graded 3C-SiC becomes available.

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On the Suitability of 3C-Silicon Carbide as an Alternative to 4H-Silicon Carbide for Power Diodes

In this article, design and characterization of the deep-trench, U-shaped field-plate (DTUFP) edge-termination structure for 1200-V-class silicon carbide (SiC) devices are presented. A systematic numerical analysis shows that the trench depth, trench width, field-plate depth, and field-plate length are the four key structural parameters to determine the voltage blocking capability of the edge-termination structure. Experimental results demonstrate that the breakdown voltage of the proposed edge-termination structure can reach 1380 V when the edge-termination structure is well designed. Liquid crystal thermal measurement and destructive breakdown testing show that the ideal planar junction breakdown voltage has been achieved. The well-designed edge-termination structure has an ultrashort-edge width of 33 $\mu \text{m}$ , which is approximately 75% shorter than that of the conventional guard-ring and junction termination extension (JTE) edge-termination structures.

Design and Characterization of the Deep-Trench, U-Shaped Field-Plate Edge Termination for 1200-V-Class SiC Devices

In this paper, a multiple-ring-modulated junction termination extension (MRM-JTE) technology for large-area silicon carbide PiN rectifier rated at 4500 V is proposed and experimentally investigated using a standard two-zone JTE (TZ-JTE) process without extra process steps or masks. Multiple modulation rings embedded inside JTE region, which is similar to varied lateral doping technology widely used in silicon devices, form a gradual decrease of effective charges in the termination region. MRM combines the advantages of two termination techniques, namely, ring-assisted JTE and space-modulated JTE, to enlarge the optimum JTE-dose window with high reverse blocking voltage in comparison with conventional TZ-JTE. A breakdown voltage of 4940 V at a leakage current of $1~\mu \text{A}$ is achieved from fabricated MRM-JTE rectifiers with a 36- $\mu \text{m}$ -thick N− epilayer doped to ${1.8} \times {10}^{{15}}$ cm−3, which is 92% of the ideal parallel-plane value. A forward current of 50 A has been measured at a forward voltage drop of 3.9 V for devices with an active anode area of 9.2 mm2, corresponding to low differential on-resistance of 1.8 $\text{m}\Omega \cdot \text {cm}^{ {2}}$ . The simulation and experimental results show that the proposed device exhibits approximately 2 times JTE dose tolerance window improvement with respect to the breakdown voltage of 4500 V.

Lijun Li

Papers

A Multiple-Ring-Modulated JTE Technique for 4H-SiC Power Device With Improved JTE-Dose Window