L
Lirida Alves de Barros Naviner
Researcher at Télécom ParisTech
Publications - 181
Citations - 1876
Lirida Alves de Barros Naviner is an academic researcher from Télécom ParisTech. The author has contributed to research in topics: Logic gate & CMOS. The author has an hindex of 21, co-authored 174 publications receiving 1505 citations. Previous affiliations of Lirida Alves de Barros Naviner include Université Paris-Saclay & Airbus.
Papers
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A Review of Sparse Recovery Algorithms
TL;DR: A comprehensive study and a state-of-the-art review of compressive sensing theory algorithms used in imaging, radar, speech recognition, and data acquisition and some open research challenges are presented.
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Compact Model of Dielectric Breakdown in Spin-Transfer Torque Magnetic Tunnel Junction
You Wang,Hao Cai,Lirida Alves de Barros Naviner,Yue Zhang,Xiaoxuan Zhao,Erya Deng,Jacques-Olivier Klein,Weisheng Zhao +7 more
TL;DR: In this paper, the physical mechanisms of time-dependent dielectric breakdown (TDDB) in an oxide barrier were analyzed and an SPICE-compact model of the MTJ was proposed.
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Signal probability for reliability evaluation of logic circuits
Denis Teixeira Franco,Denis Teixeira Franco,Maí Correia R. de Vasconcelos,Lirida Alves de Barros Naviner,Jean-François Naviner +4 more
TL;DR: The proposed methodology computes circuit’s signal reliability as a function of its logical masking capabilities, concerning multiple simultaneous faults occurrence, based on signal probability.
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Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses
You Wang,You Wang,Yue Zhang,Erya Deng,Jacques-Olivier Klein,Lirida Alves de Barros Naviner,Weisheng Zhao,Weisheng Zhao +7 more
TL;DR: A compact model of MTJ with STT stochastic behavior is proposed, in which technical variations and temperature evaluation are properly integrated and its accurate performances allow a more realistic reliability analysis involving the influences of ambient environment and technical process.
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Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology
TL;DR: This study focuses on NV logic-in-memory (LIM) architecture, exploring design space in near-threshold regime around 0.5 V supply and insights for circuit design and practical implementation of NV-LIM circuits with FD-SOI technology.