Livio Lattanzio

Bio: Livio Lattanzio is an academic researcher from École Polytechnique Fédérale de Lausanne. The author has contributed to research in topics: Field-effect transistor & Transistor. The author has an hindex of 14, co-authored 28 publications receiving 657 citations. Previous affiliations of Livio Lattanzio include École Normale Supérieure.

Complementary Germanium Electron–Hole Bilayer Tunnel FET for Sub-0.5-V Operation

Abstract: In this letter, we present a novel device, the germanium electron-hole (EH) bilayer tunnel field-effect transistor, which exploits carrier tunneling through a bias-induced EH bilayer. The proposed architecture provides a quasi-ideal alignment between the tunneling path and the electric field controlled by the gate. The device principle and performances are studied by 2-D numerical simulations. This device allows interesting features in terms of low operating voltage (<; 0.5 V), due to its super-steep subthreshold slope (SSAVG ~ 13 mV/dec over six decades of current), ION/IOFF ratio of ~ 109, and drive current of ION ~ 10 μA/μm at VDD = 0.5 V. The same structure with symmetric voltages can be used to achieve a p-type device with ION and IOFF levels comparable to the n-type, which enables a straightforward implementation of complementary logic that could theoretically reach a maximum operating frequency of 1.39 GHz when VDD = 0.25 V.

Understanding the Superlinear Onset of Tunnel-FET Output Characteristic

Abstract: In this letter, we report that the source and channel Fermi-Dirac distributions in interband-tunneling-controlled transistors play a fundamental role on the modulation of the injected current. We explain the superlinear onset of the output characteristics based on the occupancy function modulation. Thus, we point out that, along with the tunneling barrier transparency, the availability of carriers and empty states, at the beginning and at the end of the tunneling path, respectively, should be always taken into account for a proper modeling of tunnel FETs.

The electron–hole bilayer tunnel FET

Abstract: We propose a novel tunnel field-effect transistor (TFET) concept called the electron–hole bilayer TFET (EHBTFET). This device exploits the carrier tunneling through a bias-induced electron–hole bilayer in order to achieve improved switching and higher drive currents when compared to a lateral p–i–n junction TFET. The device principle and performances are studied by 2D numerical simulations. Output and transfer characteristics, as well as the impact of back gate bias, silicon thickness and gate length on the device behavior are evaluated. Device performances are compared for Si and Ge implementations. Nearly ideal average subthreshold slope (SSavg ∼ 10 mV/dec over 7 decades of current) and Ion/Ioff > 10^8 at Vd = Vg = 0.5 V are obtained, due to the OFF–ON binary transition which leads to the abrupt onset of the band-to-band tunneling inside the semiconductor channel. Remarkably, for Ge EHBTFETs the Ion (∼11 μA/μm at Vdd = 0.5 V) is 10× larger than in Ge tunnel FETs and 380× larger than in Si EHBTFETs.

Electron-hole bilayer tunnel FET for steep subthreshold swing and improved ON current

Abstract: We propose a novel Tunnel field-effect transistor (TFET) concept called the electron-hole bilayer TFET (EHBTFET). This device exploits the carrier tunneling through a bias-induced electron-hole bilayer in order to achieve improved switching and higher drive currents when compared to a lateral p-i-n junction TFET. The device principle and performances are studied by 2D numerical simulations. Output and transfer characteristics, as well as the impact of back gate bias, silicon thickness and gate length on the device behavior are evaluated. Near ideal average subthreshold slope (SS AVG ∼ 12 mV/dec over 6 decades of current) and I ON /I off > 108 at V D = V G = 0.5 V figures of merit are obtained, due to the OFF-ON binary transition which leads to the abrupt onset of the band-to-band tunneling inside the silicon channel. Drive current (I ON ) in the EHBTFET is 3× higher that in traditional all-Si Tunnel FET but below 0.1 μA/μm.

Tunneling and Occupancy Probabilities: How Do They Affect Tunnel-FET Behavior?

Abstract: In this letter, the occupancy and tunneling probabilities of interband tunneling devices are studied, pointing out the fundamental function of the source Fermi-Dirac distribution. Particularly, the reason for the degraded subthreshold swing, which is typical of devices with highly doped source, is explained, and its relation with the high-energy source Fermi tail is carefully analyzed. Simultaneously, the poor driving capability of Tunnel-FET devices is investigated, highlighting the primary role played by the occupancy functions.

Tunnel field-effect transistors as energy-efficient electronic switches

Abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel Field-Effect Transistors: State-of-the-Art

Abstract: Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowest values are not based on many points. The highest current at which sub-threshold swing below 60 mV/decade is observed is in the range 1–10 nA/ \({{\mu }}\) m. A common approach to TFET characterization is proposed to facilitate future comparisons.

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Abstract: Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Furthermore, fabrication of doping-less TFET does not require a high-temperature doping/annealing processes and therefore cuts down the thermal budget, opening up possibilities for fabricating TFETs on single crystal silicon-on-glass substrates formed by wafer scale epitaxial transfer.

Demonstration of L-Shaped Tunnel Field-Effect Transistors

Abstract: An L-shaped tunnel FET (TFET), which features band-to-band tunneling (BTBT) perpendicular to the channel direction, is experimentally demonstrated for the first time. It is more scalable than other vertical-BTBT-based TFET designs and provides more than $1000\times $ higher ON-current ( $I_{{\mathrm{\scriptscriptstyle ON}}}$ ) than a conventional planar TFET with the same gate overdrive ( $V_{\mathrm{ov}}$ ) of 0.8 V, due to improved subthreshold swing ( $S$ ) and larger tunnel junction area. Its temperature dependence, constant $S$ , and nonlinear output characteristics are discussed.

III–V compound semiconductor transistors—from planar to nanowire structures

Abstract: Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III–V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III–V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III–V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III–V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS applications.