L
Lixin Ge
Researcher at Qualcomm
Publications - 29
Citations - 178
Lixin Ge is an academic researcher from Qualcomm. The author has contributed to research in topics: Transistor & Layer (electronics). The author has an hindex of 7, co-authored 29 publications receiving 158 citations.
Papers
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Journal ArticleDOI
FinFET SRAM Optimization With Fin Thickness and Surface Orientation
Mingu Kang,S. C. Song,S. H. Woo,Hyun-Kook Park,Mohamed Hassan Abu-Rahma,Lixin Ge,Beom-Mo Han,Joseph Wang,Geoffrey Yeap,Seong-Ook Jung +9 more
TL;DR: In this article, the design space, including fin thickness, fin height, fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints.
Patent
Stable SRAM Bitcell Design Utilizing Independent Gate Finfet
Seong-Ook Jung,Mingu Kang,Hyunkook Park,S. C. Song,Mohamed Hassan Abu-Rahma,Beom-Mo Han,Lixin Ge,Zhongze Wang +7 more
TL;DR: In this paper, the authors propose to adjust drive strengths of pull-up and pass-gate devices during read and write operations to improve RSNM and WNM by adjusting drive strengths during read-and write operations.
Proceedings ArticleDOI
Cost effective 28nm LP SoC technology optimized with circuit/device/process co-design for smart mobile devices
P. Chidambaram,Chock H. Gan,S. Sengupta,Lixin Ge,Ying Chen,Sam Yang,Ping Liu,Joseph Wang,Ming-Ta Yang,Charles Teng,Yang Du,Prayag B. Patel,Pratyush Kamal,R. Bucki,Foua Vang,Animesh Datta,K. R. Bellur,Sei Seung Yoon,N. Chen,Aaron Thean,Michael Han,Esin Terzioglu,Xuefeng Zhang,J. Fischer,Mehdi Hamidi Sani,B. Flederbach,Geoffrey Yeap +26 more
TL;DR: In this paper, a cost effective 28 nm 4G SOC technology has been crafted using two sets of design rules and 7 different Vt cells with optimal power gating to achieve a 2.4× increase in gate density, 55% decrease in power and 30% gain in frequency with respect to the 45 nm counterpart.
Patent
Low-power 5t sram with improved stability and reduced bitcell size
Seong-Ook Jung,Hyun-Kook Park,S. C. Song,Mohamed Hassan Abu-Rahma,Lixin Ge,Zhongze Wang,Beom-Mo Han +6 more
TL;DR: In this article, a 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation, which includes a storage element for storing data, wherein the storage element is coupled a first voltage and a ground voltage.
Proceedings Article
Non-Gaussian distribution of SRAM read current and design impact to low power memory using Voltage Acceleration Method
Joseph Wang,Ping Liu,Yandong Gao,Pankaj Deshmukh,Sam Yang,Ying Chen,Wing Sy,Lixin Ge,Esin Terzioglu,Mohamed Hassan Abu-Rahma,Manish Garg,Sei Seung Yoon,Michael Han,Mehdi Hamidi Sani,Geoffrey Yeap +14 more
TL;DR: Data shows that conventional assumption of Gaussian distribution in read current is inaccurate especially at low Vdd and cold temperature conditions for low power memory in 28nm and beyond technology nodes.