Luca Cassano

TL;DR: A fully distributed charge equalizer based on a circular balancing bus, which outperforms other recently published approaches and formally been verified using a model checker, showing that formal methods and, in particular, the Symbolic Analysis Laboratory environment, can be effective to verify the safety requirements of a BMS.

TL;DR: The main contribution of this paper is an overview of the existing design standards that regulate the design and verification of FPGA-based systems in safety-critical application fields and a survey of significant published research proposals and existing industrial guidelines about the topic.

TL;DR: An accurate simulation method is presented for the evaluation of the effects of SEUs in the configuration memory of SRAM-based FPGAs and results predict almost completely the results obtained through fault injection.

TL;DR: GABES, a tool for the generation of test patterns for application-dependent testing of SEUs in SRAM-FPGAs, based on a genetic algorithm, suggests that this approach may be effective in the inspection of safety-critical components of control systems implemented on FPGAs.

TL;DR: A simulator of soft errors in the configuration memory of SRAM-based FPGAs, named ASSESS, adopts fault models for SEUs affecting the configuration bits controlling both logic and routing resources that have been demonstrated to be much more accurate than classical fault models adopted by academic and industrial fault simulators currently available.