Luca Sayadi

Bio: Luca Sayadi is an academic researcher from University of Pisa. The author has contributed to research in topics: Exponential function & Transistor. The author has an hindex of 2, co-authored 2 publications receiving 89 citations.

Threshold Voltage Instability in p-GaN Gate AlGaN/GaN HFETs

Abstract: We investigate the impact of the gate contact on the threshold voltage stability in p-GaN gate AlGaN/GaN heterojunction field-effect transistors with double pulse measurements on the p-GaN gate devices and device simulations. We find that, under gate stress, in the case of high-leakage Schottky contact, a negative threshold voltage shift results from hole accumulation in the p-GaN region. Conversely, in the case of low-leakage Schottky contact, hole depletion in the p-GaN region gives rise to a positive threshold voltage shift. More generally, we show that an imbalance between the hole tunneling current through the Schottky barrier and the thermionic current across the AlGaN barrier results in a variation of the total charge stored in the p-GaN region, which in turn is responsible for the observed threshold voltage shift. Finally, we present a simplified equivalent circuit model for the p-GaN gate module.

The Role of Silicon Substrate on the Leakage Current Through GaN-on-Si Epitaxial Layers

Abstract: We present an investigation of vertical leakage in GaN-on-Si epitaxial stack through electrical characterization and device simulations. Different structures of increasing complexity have been fabricated and analyzed in order to achieve a complete understanding of the main transport mechanisms. We have clarified the role of the Si substrate through comparison of identical structures built on p-type and n-type Si substrates. We show that in the case of p-Si substrates the leakage current is sustained by carrier generation in the Si depletion region. We also find that experiments on structures grown on n-doped silicon are consistent with considering electron injection from the substrate through the AlN/Si barrier as the main current limiting mechanism. Our insights are supported by device simulations that consistently reproduce the experimental capacitance–voltage and current–voltage characteristics as a function of temperature for all the considered structures.

Trap-state mapping to model GaN transistors dynamic performance

Abstract: Trapping phenomena degrade the dynamic performance of wide-bandgap transistors. However, the identification of the related traps is challenging, especially in presence of non-ideal defects. In this paper, we propose a novel methodology (trap-state mapping) to extract trap parameters, based on the mathematical study of stretched exponential recovery kinetics. To demonstrate the effectiveness of the approach, we use it to identify the properties of traps in AlGaN/GaN transistors, submitted to hot-electron stress. After describing the mathematical framework, we demonstrate that the proposed methodology can univocally describe the properties of the distribution of trap states. In addition, to prove the validity and the usefulness of the model, the trap properties extracted mathematically are used as input for TCAD simulations. The results obtained by TCAD closely match the experimental transient curves, thus confirming the accuracy of the trap-state mapping procedure. This methodology can be adopted also on other technologies, thus constituting a universal approach for the analysis of multiexponential trapping kinetics.

Modeling Hot-Electron Trapping in GaN-based HEMTs

Abstract: Hot electron trapping can significantly impact the performance of GaN-based HEMTs. Within this paper, the effect of current density and electric field on the severity of hot electron degradation is presented. The experiments demonstrate that: (i) we can isolate the hot electron trapping processes, (ii) the hot-electron induced performance degradation follows a logarithmic kinetic, which can be modeled by rate equations, and (iii) the amount of current collapse has a linear dependence on the applied electric field and a logarithmic dependence on the current density, in agreement with theoretical equations.

On the CET-Map Ill-Posed Inversion Problem: Theory and Application to GaN HEMTs

Abstract: Ideally, de-trapping transients in semiconductors originate from discrete energy levels, and the emission profile follows a pure exponential decay; however, it has been widely shown that this rarely happens in real devices, for which capture and emission processes have a strongly stretched exponential shape. Conventional methodologies for capture/emission time constants mapping (CET maps) are based on the double derivative (DD) or bivariate Gaussian (BG) approximation, which may lead to inaccuracies in the presence of complex defect distributions. In this article, we introduce a new methodology, based on the double inverse Laplace transform, to extract the accurate capture-emission time (CET) map of these defects. The proposed approach is compared with the conventional approximated solutions, thus giving insight into whether the error introduced by the simplified approaches can be considered negligible or not. First, to ensure full control of the input parameters, the analysis is carried out on custom-generated functions with different stretching parameters. Then, the developed methodology is used to extract, for the first time, the full capture/emission time map from a power GaN high-electron mobility transistor (HEMT) subjected to positive bias instability (PBI) test. The proposed approach is universal and can be adopted by a wide variety of electronic devices in the presence of charge-trapping processes.

GaN-based power devices: Physics, reliability, and perspectives

Abstract: Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semiconductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spontaneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high-voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench-structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main properties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics.

An Overview of Normally-Off GaN-Based High Electron Mobility Transistors.

Abstract: Today, the introduction of wide band gap (WBG) semiconductors in power electronics has become mandatory to improve the energy efficiency of devices and modules and to reduce the overall electric power consumption in the world. Due to its excellent properties, gallium nitride (GaN) and related alloys (e.g., AlxGa1−xN) are promising semiconductors for the next generation of high-power and high-frequency devices. However, there are still several technological concerns hindering the complete exploitation of these materials. As an example, high electron mobility transistors (HEMTs) based on AlGaN/GaN heterostructures are inherently normally-on devices. However, normally-off operation is often desired in many power electronics applications. This review paper will give a brief overview on some scientific and technological aspects related to the current normally-off GaN HEMTs technology. A special focus will be put on the p-GaN gate and on the recessed gate hybrid metal insulator semiconductor high electron mobility transistor (MISHEMT), discussing the role of the metal on the p-GaN gate and of the insulator in the recessed MISHEMT region. Finally, the advantages and disadvantages in the processing and performances of the most common technological solutions for normally-off GaN transistors will be summarized.

Charge Storage Mechanism of Drain Induced Dynamic Threshold Voltage Shift in ${p}$ -GaN Gate HEMTs

Abstract: The drain induced dynamic threshold voltage ( ${V}_{\textrm {th}}$ ) shift of a ${p}$ -GaN gate HEMT with a Schottky gate contact is investigated, and the underlying mechanisms are explained with a charge storage model. When the device experiences a high drain bias ${V}_{\textrm {DSQ}}$ , the gate-to-drain capacitance ( ${C}_{\textrm {GD}}$ ) is charged to ${Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSQ}}$ ). As the drain voltage drops to ${V}_{\textrm {DSM}}$ where ${V}_{\textrm {th}}$ is measured, ${C}_{\textrm {GD}}$ is expected to be discharged to ${Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSM}}$ ). However, the metal/ ${p}$ -GaN Schottky junction could block the discharging current, resulting in storage of negative charges in the ${p}$ -GaN layer. For the device to turn on, additional gate voltage is required to counteract the stored negative charges, resulting in a positive shift of ${V}_{\textrm {th}}$ . The dynamic ${V}_{\textrm {th}}$ shift is an intrinsic and predictable characteristic of the ${p}$ -GaN gate HEMT which is linearly correlated with $\Delta \!{Q}_{\textrm {GD}}={Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSQ}}$ ) $- {Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSM}}$ ). The ${V}_{\textrm {th}}$ shift is dependent on ${V}_{\textrm {DSQ}}$ as well as ${V}_{\textrm {DSM}}$ , indicating that the ${V}_{\textrm {th}}$ shift is varying along the load line during a switching operation.

V TH Instability of ${p}$ -GaN Gate HEMTs Under Static and Dynamic Gate Stress

Abstract: The impacts of static and dynamic gate stress on the threshold voltage ( ${V}_{\text {TH}}$ ) instability in Schottky-type ${p}$ -GaN gate AlGaN/GaN heterojunction field-effect transistors are experimentally investigated. ${V}_{\text {TH}}$ shifts negatively under large positive bias static stress ( ${V}_{\text {G}}\_ {\text {stress}} > 5$ V) by adopting conventional quasi-static characterization techniques. In contrast, ${V}_{\text {TH}}$ under fast-dynamic-stress exhibits positive shift, and a positive frequency dependence occurs within a wide range of frequency from 10 Hz to 1 MHz. The different ${V}_{\text {TH}}$ instability behavior under static and dynamic stress mainly originates from the time-dependent charges (electrons and holes) storage/release mechanisms in the ${p}$ -GaN layer, which is floating in the Schottky-type ${p}$ -GaN gate HEMT.