[신간의 별자리x] 우리/미술, 그리고 ‘슬픔의 박물관’

The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Electronics based on two-dimensional materials

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

where A represents the magnetic vector potential, is an integral of the hydromagnetic equations. This -integral made it possible to formulate a variational principle for the force-free magnetic fields. The integral expresses the fact that motions cannot transform a given field in an entirely arbitrary different field, if the conductivity of the medium isconsidered infinite. In this paper we shall show that the full set of hydromagnetic equations admit five more integrals, besides the energy integral, if dissipative processes are absent. These integrals, as we shall presently verify, are I2 =fbHvdV, (2)

Proceedings of the National Academy of Sciences

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher on-currents of n- and p-TFETs of > 10 μA/μm at VDS=0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <; 60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very lowVDD=0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD=1.0 V.

Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

In this paper, we have extensively investigated the silicon thickness dependence of the low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single- and in double-gate mode. A physically based model including all the scattering mechanisms that are known to be most relevant in bulk MOSFETs has been extended and applied to SOI structures. A systematic comparison with the measurements shows that the experimental mobility dependence on the silicon thickness (T/sub SI/) cannot be quantitatively explained within the transport picture that seems adequate for bulk transistors. In an attempt to improve the agreement with the experiments, we have critically rediscussed our model for the phonon scattering and developed a model for the scattering induced by the T/sub SI/ fluctuations. Our results suggest that the importance of the surface optical (SO) phonons could be significantly enhanced in UT-SOI MOSFETs with respect to bulk transistors. Furthermore, both the SO phonon and the T/sub SI/ fluctuation scattering are remarkably enhanced with reducing T/sub SI/, so that they could help explain the experimental mobility behavior.

Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs

In this paper, and in Part II, Monte Carlo (MC) simulations including quantum corrections to the potential and calibrated scattering models are used to study electronic transport in bulk and double-gate silicon-on-insulator MOSFETs with L/sub G/ down to 14-nm designed according to the 2003 International Technology Roadmap for Semiconductors. Simulations with and without scattering are used to assess the influence of quasi-ballistic transport on the MOSFET on-current. We analyze in detail the flux of back-scattered carriers. The role of scattering in different parts of the device is clarified and the MC results are compared to simple models for quasi-ballistic transport presented in the literature.

Understanding quasi-ballistic transport in nano-MOSFETs: part I-scattering in the channel and in the drain

1. Introduction 2. Bulk semiconductors and the semi-classical model 3. Quantum confined inversion layers 4. Carrier scattering in silicon MOS transistors 5. The Boltzmann transport equation 6. The Monte Carlo method for the Boltzmann transport equation 7. Simulation of bulk and SOI silicon MOSFETs 8. MOS transistors with arbitrary crystal orientation 9. MOS transistors with strained silicon channels 10. MOS transistors with alternative materials Appendix A. Mathematical definitions and properties Appendix B. Integrals and transformations over a finite area A Appendix C. Calculation of the equi-energy lines with the k-p model Appendix D. Matrix elements beyond the envelope function approximation Appendix E. Charge density produced by a perturbation potential.

Nanoscale MOS Transistors: Semi-Classical Transport and Applications

In this paper, we present a comprehensive experimental characterization of electron and hole effective mobility (/spl mu//sub eff/) of ultrathin SOI n- and p-MOSFETs. Measurements have been performed at different temperatures using a special test structure able to circumvent parasitic resistance effects. Our results indicate that, at large inversion densities (N/sub inv/), the mobility of ultrathin SOI transistors is largely insensitive to silicon thickness (T/sub SI/) and is larger than in heavily doped bulk MOS because of a lower effective field. At small N/sub inv/, instead, mobility of SOI transistors exhibits a systematic reduction with decreasing T/sub SI/. The possible explanation for this /spl mu//sub eff/ degradation in extremely thin silicon layers is discussed by means of a comparison to previously published experimental data and theoretical calculations. Our analysis suggests a significant role is played by an enhancement of phonon scattering due to carrier confinement in the thinnest semiconductor films. The experimental mobility data have then been used to study the possible implications for ultrashort SOI transistor performance using numerical simulations.

Luca Selmi

Papers

Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs

Understanding quasi-ballistic transport in nano-MOSFETs: part I-scattering in the channel and in the drain

Nanoscale MOS Transistors: Semi-Classical Transport and Applications

Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application