Showing papers by "Luca Sterpone published in 2004"
12 Jul 2004
TL;DR: A fault-injection environment developed at this institution is exploited to analyze the impact of single event upsets affecting the configuration memory of SRAM-based FPGAs when fault tolerant design techniques are adopted, and shows that the TMR design technique mainly depends on the characteristics of the adopted TMR architecture in terms of placing and routing.
Abstract: The growing adoption of SRAM-based field programmable gate arrays (FPGAs) in safety-critical applications demands for efficient methodologies for evaluating their reliability. Single event upsets (SEUs) affecting the configuration memory of SRAM-based FPGAs are a major concern, since they can permanently affect the function implemented by the device. We exploited a fault-injection environment developed at our institution to analyze the impact of such faults on SRAM-based FPGAs when fault tolerant design techniques are adopted. The experimental results allow quantitative evaluations of the effects of these faults, and show that the sensitivity of the TMR design technique mainly depends on the characteristics of the adopted TMR architecture in terms of placing and routing.
61 citations
TL;DR: A new approach for predicting SEU effects in circuits mapped on SRAM-based FPGAs that combines radiation testing with simulation is described, which is used to characterize (in terms of device cross section) the technology on which the FPGA device is based, no matter which circuit it implements.
Abstract: SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets (SEUs) that, by changing the FPGA's configuration memory, may affect dramatically the functions implemented by the device. In This work we describe a new approach for predicting SEU effects in circuits mapped on SRAM-based FPGAs that combines radiation testing with simulation. The former is used to characterize (in terms of device cross section) the technology on which the FPGA device is based, no matter which circuit it implements. The latter is used to predict the probability for a SEU to alter the expect behavior of a given circuit. By combining the two figures, we then compute the cross section of the circuit mapped on the pre-characterized device. Experimental results are presented that compare the approach we developed with a traditional one based on radiation testing only, to measure the cross section of a circuit mapped on an FPGA. The figures here reported confirm the accuracy of our approach.
51 citations